debug-halt-step-fsm

// Control block: stops/resumes a core over a debug port.
//
// All outputs are registered. Reset is synchronous, active-high, and clears
// all state and outputs to 0. Convention used below: "value at edge N" is the
// registered value produced by the update on edge N (i.e. sampled just after
// that edge). The FSM continues issuing fetches for one extra cycle after a
// halt request, so halted_o first asserts two edges after the request.
module TopModule (
    input  logic       clk,
    input  logic       rst,
    input  logic       halt_req_i,
    input  logic       resume_req_i,
    input  logic       step_req_i,
    input  logic       dbus_ren_i,
    input  logic [1:0] dbus_addr_i,
    output logic [7:0] dbus_rdata_o,
    output logic       halted_o,
    output logic       fetch_o
);

    // -----------------------------------------------------------------
    // Run/halt/step/resume control FSM
    // -----------------------------------------------------------------
    // State encoding
    localparam logic [2:0] RUNNING = 3'd0, // fetching, not halted
                           HALT1   = 3'd1, // extra fetch cycle after halt req
                           HALTED  = 3'd2, // stopped
                           STEP1   = 3'd3, // one cycle before single-step fetch
                           STEP2   = 3'd4, // single-step fetch pulse
                           RESUME1 = 3'd5; // one cycle before resuming

    logic [2:0] state;

    always_ff @(posedge clk) begin
        if (rst) begin
            state    <= RUNNING;
            fetch_o  <= 1'b0;
            halted_o <= 1'b0;
        end else begin
            case (state)
                RUNNING: begin
                    // Continue fetching this cycle regardless; on a halt
                    // request take one more fetch cycle before stopping.
                    fetch_o  <= 1'b1;
                    halted_o <= 1'b0;
                    state    <= halt_req_i ? HALT1 : RUNNING;
                end

                HALT1: begin
                    // Last fetch cycle; halted_o asserts next edge.
                    fetch_o  <= 1'b1;
                    halted_o <= 1'b0;
                    state    <= HALTED;
                end

                HALTED: begin
                    fetch_o  <= 1'b0;
                    halted_o <= 1'b1;
                    // halt_req_i suppresses a simultaneous step_req_i: the
                    // core simply stays halted with fetch low.
                    if (step_req_i && !halt_req_i)
                        state <= STEP1;
                    else if (resume_req_i)
                        state <= RESUME1;
                    else
                        state <= HALTED;
                end

                STEP1: begin
                    // Deliver the single-step fetch pulse next edge.
                    fetch_o  <= 1'b1;
                    halted_o <= 1'b0;
                    state    <= STEP2;
                end

                STEP2: begin
                    // Fall back into the halted state.
                    fetch_o  <= 1'b0;
                    halted_o <= 1'b1;
                    state    <= HALTED;
                end

                RESUME1: begin
                    fetch_o  <= 1'b1;
                    halted_o <= 1'b0;
                    state    <= RUNNING;
                end

                default: begin
                    fetch_o  <= 1'b0;
                    halted_o <= 1'b0;
                    state    <= RUNNING;
                end
            endcase
        end
    end

    // -----------------------------------------------------------------
    // Debug-bus read (independent of the FSM, works in any state)
    // -----------------------------------------------------------------
    // A read request (dbus_ren_i high, address A) sampled at edge R presents
    // location A on dbus_rdata_o at edge R+1, then holds while dbus_ren_i is
    // low. The request is registered one stage so the data appears one edge
    // after the request edge.
    logic [1:0] addr_q;
    logic       ren_q;

    always_ff @(posedge clk) begin
        if (rst) begin
            dbus_rdata_o <= 8'h00;
            addr_q       <= 2'b00;
            ren_q        <= 1'b0;
        end else begin
            ren_q  <= dbus_ren_i;
            addr_q <= dbus_addr_i;
            if (ren_q) begin
                case (addr_q)
                    2'd0:    dbus_rdata_o <= 8'h5A;
                    2'd1:    dbus_rdata_o <= 8'hC3;
                    2'd2:    dbus_rdata_o <= 8'h0F;
                    default: dbus_rdata_o <= 8'h96; // addr 3
                endcase
            end
            // else: hold previous value
        end
    end

endmodule