dualmaster-membridge

module TopModule (
    input  logic        clk,
    input  logic        rst,
    input  logic        a_req_i,
    input  logic [7:0]  a_addr_i,
    output logic        a_ack_o,
    output logic [15:0] a_data_o,
    input  logic        b_req_i,
    input  logic [7:0]  b_addr_i,
    output logic        b_ack_o,
    output logic [15:0] b_data_o,
    output logic        m_req_o,
    output logic [7:0]  m_addr_o,
    input  logic [15:0] m_data_i
);
    // Operation phases relative to the sample edge E:
    //   IDLE = cycle E     : nothing driven, request sampled at this edge
    //   REQ  = cycle E+1   : m_req_o/m_addr_o carry the command
    //   W1   = cycle E+2
    //   W2   = cycle E+3   : m_data_i is valid, captured on the edge into ACK
    //   ACK  = cycle E+4   : winner's ack + word driven
    //   back to IDLE at E+5
    localparam logic [2:0] IDLE=3'd0, REQ=3'd1, W1=3'd2, W2=3'd3, ACK=3'd4;

    logic [2:0] state;
    logic       a_req_r, b_req_r;   // requests seen one cycle earlier
    logic       post_op;            // high only during the E+5 idle cycle
    logic       have_last;          // a recent winner exists (hot priority)
    logic       last_winner;        // 0 = A, 1 = B
    logic       win;                // winner of the in-flight operation

    // Arbitration.  A fresh arrival must be present for a full idle cycle
    // before it can be sampled (registered one idle cycle before E); the
    // sample directly after an operation (post_op) acts on the current
    // request immediately.
    logic a_q, b_q, sample_now, winner;
    always_comb begin
        if (post_op) begin
            a_q = a_req_i;
            b_q = b_req_i;
        end else begin
            a_q = a_req_i & a_req_r;
            b_q = b_req_i & b_req_r;
        end
        sample_now = a_q | b_q;
        if (a_q && b_q)
            winner = have_last ? ~last_winner : 1'b0; // hot: not-last-winner; cold: A
        else if (a_q)
            winner = 1'b0;
        else
            winner = 1'b1;
    end

    always_ff @(posedge clk) begin
        if (rst) begin
            state       <= IDLE;
            a_req_r     <= 1'b0;
            b_req_r     <= 1'b0;
            post_op     <= 1'b0;
            have_last   <= 1'b0;
            last_winner <= 1'b0;
            win         <= 1'b0;
            a_ack_o     <= 1'b0;
            a_data_o    <= 16'd0;
            b_ack_o     <= 1'b0;
            b_data_o    <= 16'd0;
            m_req_o     <= 1'b0;
            m_addr_o    <= 8'd0;
        end else begin
            a_req_r <= a_req_i;
            b_req_r <= b_req_i;

            // one-shot outputs default low each cycle
            m_req_o  <= 1'b0;
            m_addr_o <= 8'd0;
            a_ack_o  <= 1'b0;
            a_data_o <= 16'd0;
            b_ack_o  <= 1'b0;
            b_data_o <= 16'd0;
            post_op  <= 1'b0;

            case (state)
                IDLE: begin
                    if (sample_now) begin
                        win         <= winner;
                        last_winner <= winner;
                        have_last   <= 1'b1;
                        m_req_o     <= 1'b1;
                        m_addr_o    <= winner ? b_addr_i : a_addr_i;
                        state       <= REQ;
                    end else begin
                        have_last <= 1'b0;   // idle stretch resets the bias
                        state     <= IDLE;
                    end
                end
                REQ: state <= W1;
                W1:  state <= W2;
                W2: begin
                    if (win == 1'b0) begin
                        a_ack_o  <= 1'b1;
                        a_data_o <= m_data_i;
                    end else begin
                        b_ack_o  <= 1'b1;
                        b_data_o <= m_data_i;
                    end
                    state <= ACK;
                end
                ACK: begin
                    post_op <= 1'b1;
                    state   <= IDLE;
                end
                default: state <= IDLE;
            endcase
        end
    end
endmodule