coprocessor-dispatcher-classmix

module TopModule (
    input  logic        clk,
    input  logic        rst,
    input  logic        op_valid_i,
    input  logic [1:0]  op_class_i,
    input  logic [1:0]  op_rd_i,
    input  logic [15:0] op_data_i,
    input  logic        c2_done_i,
    output logic        op_accept_o,
    output logic        wb_valid_o,
    output logic [1:0]  wb_rd_o,
    output logic [15:0] wb_data_o,
    output logic        c2_busy_o,
    output logic [3:0]  inflight_o
);

    // One slot per class (0, 1, 2)
    logic        s0_v, s1_v, s2_v;      // occupied
    logic [1:0]  s0_rd, s1_rd, s2_rd;   // destination
    logic [15:0] s0_data, s1_data, s2_data; // precomputed writeback data
    logic        s1_aged;   // class 1: set one cycle after accept -> ready
    logic        s2_ready;  // class 2: sticky ready once c2_done_i seen

    // --- Combinational accept ---------------------------------------------
    logic slot_empty;
    always_comb begin
        case (op_class_i)
            2'd0:    slot_empty = ~s0_v;
            2'd1:    slot_empty = ~s1_v;
            2'd2:    slot_empty = ~s2_v;
            default: slot_empty = 1'b0; // class 3: never accepted
        endcase
    end

    assign op_accept_o = op_valid_i && (op_class_i != 2'd3) &&
                         !inflight_o[op_rd_i] && slot_empty;

    // c2_busy_o: high exactly while the class-2 slot is occupied
    assign c2_busy_o = s2_v;

    // --- Ready / arbitration (combinational, priority 0 > 1 > 2) ----------
    logic ready0, ready1, ready2;
    logic do_wb0, do_wb1, do_wb2;
    assign ready0 = s0_v;               // class 0 ready as soon as occupied
    assign ready1 = s1_v & s1_aged;     // class 1 ready one cycle after accept
    assign ready2 = s2_v & s2_ready;    // class 2 ready once c2_done_i seen
    assign do_wb0 = ready0;
    assign do_wb1 = ready1 & ~do_wb0;
    assign do_wb2 = ready2 & ~do_wb0 & ~do_wb1;

    // --- Sequential -------------------------------------------------------
    always_ff @(posedge clk) begin
        if (rst) begin
            s0_v      <= 1'b0; s1_v    <= 1'b0; s2_v    <= 1'b0;
            s0_rd     <= 2'd0; s1_rd   <= 2'd0; s2_rd   <= 2'd0;
            s0_data   <= 16'd0; s1_data <= 16'd0; s2_data <= 16'd0;
            s1_aged   <= 1'b0;
            s2_ready  <= 1'b0;
            wb_valid_o <= 1'b0;
            wb_rd_o    <= 2'd0;
            wb_data_o  <= 16'd0;
            inflight_o <= 4'd0;
        end else begin
            wb_valid_o <= 1'b0; // default: pulse only

            // Class 1 aging: becomes ready the cycle after accept
            if (s1_v) s1_aged <= 1'b1;
            // Class 2 sticky readiness
            if (s2_v && c2_done_i) s2_ready <= 1'b1;

            // Writeback: at most one per cycle, priority 0 > 1 > 2.
            // Blocked (lower-priority) slots keep their valid/ready state.
            if (do_wb0) begin
                wb_valid_o <= 1'b1;
                wb_rd_o    <= s0_rd;
                wb_data_o  <= s0_data;
                s0_v       <= 1'b0;
                inflight_o[s0_rd] <= 1'b0;
            end else if (do_wb1) begin
                wb_valid_o <= 1'b1;
                wb_rd_o    <= s1_rd;
                wb_data_o  <= s1_data;
                s1_v       <= 1'b0;
                inflight_o[s1_rd] <= 1'b0;
            end else if (do_wb2) begin
                wb_valid_o <= 1'b1;
                wb_rd_o    <= s2_rd;
                wb_data_o  <= s2_data;
                s2_v       <= 1'b0;
                s2_ready   <= 1'b0;
                inflight_o[s2_rd] <= 1'b0;
            end

            // Accept / store on the accepting edge.
            // (A slot writing back this cycle is still occupied, so a new
            //  request to that class is rejected -> no collision.  The
            //  accepted destination cannot equal a writing-back destination
            //  because accept requires !inflight_o[op_rd_i].)
            if (op_accept_o) begin
                inflight_o[op_rd_i] <= 1'b1;
                case (op_class_i)
                    2'd0: begin
                        s0_v    <= 1'b1;
                        s0_rd   <= op_rd_i;
                        s0_data <= op_data_i + 16'd1;
                    end
                    2'd1: begin
                        s1_v    <= 1'b1;
                        s1_rd   <= op_rd_i;
                        s1_data <= op_data_i << 1;   // op_data_i * 2 (mod 2^16)
                        s1_aged <= 1'b0;
                    end
                    2'd2: begin
                        s2_v     <= 1'b1;
                        s2_rd    <= op_rd_i;
                        s2_data  <= op_data_i ^ 16'hffff;
                        s2_ready <= 1'b0;
                    end
                    default: ; // class 3 unreachable (op_accept_o forces !=3)
                endcase
            end
        end
    end

endmodule