stream-frame-hold

module TopModule (
    input  wire        clk,
    input  wire        rst,
    input  wire        wr_i,
    input  wire [31:0] wr_data,
    input  wire        wr_last_i,
    output wire        wr_ready_o,
    output reg         m_tvalid_o,
    output reg  [31:0] m_tdata_o,
    output reg         m_tlast_o,
    input  wire        m_tready_i
);

    // Depth-8 FIFO storing {last, data}
    reg [32:0] mem [0:7];
    reg [2:0]  head;
    reg [2:0]  tail;
    reg [3:0]  count;

    // Output-side state
    reg        cur_triggers_pad;  // current valid beat is a payload with last=1
    reg [1:0]  pads_remaining;    // number of pad beats still to emit
    reg [31:0] last_payload;      // data of the last payload (for pad generation)

    // Ready when FIFO not full (and not in reset)
    assign wr_ready_o = (count != 4'd8) && ~rst;

    // Combined occupancy events
    wire do_push = wr_i && wr_ready_o;
    wire do_pop  = (~m_tvalid_o) && (pads_remaining == 2'd0) && (count != 4'd0);

    always @(posedge clk) begin
        if (rst) begin
            head             <= 3'd0;
            tail             <= 3'd0;
            count            <= 4'd0;
            m_tvalid_o       <= 1'b0;
            m_tdata_o        <= 32'd0;
            m_tlast_o        <= 1'b0;
            cur_triggers_pad <= 1'b0;
            pads_remaining   <= 2'd0;
            last_payload     <= 32'd0;
        end else begin
            // ---- FIFO push ----
            if (do_push) begin
                mem[tail] <= {wr_last_i, wr_data};
                tail      <= tail + 3'd1;
            end

            // ---- Output / pop logic ----
            if (m_tvalid_o) begin
                // A beat is presented; hold until accepted.
                if (m_tready_i) begin
                    // xfer: deassert valid (one idle cycle before next load)
                    m_tvalid_o <= 1'b0;
                    if (cur_triggers_pad) begin
                        pads_remaining <= 2'd2;
                        last_payload   <= m_tdata_o;
                    end
                end
                // else: hold data/last/valid unchanged
            end else begin
                // Valid is low: load the next beat (pads take priority)
                if (pads_remaining != 2'd0) begin
                    m_tvalid_o       <= 1'b1;
                    m_tdata_o        <= last_payload ^ 32'h0BAD_F00D;
                    m_tlast_o        <= (pads_remaining == 2'd1); // second pad
                    cur_triggers_pad <= 1'b0;
                    pads_remaining   <= pads_remaining - 2'd1;
                end else if (count != 4'd0) begin
                    m_tvalid_o       <= 1'b1;
                    m_tdata_o        <= mem[head][31:0];
                    m_tlast_o        <= 1'b0;                 // payload beats: tlast=0
                    cur_triggers_pad <= mem[head][32];
                    head             <= head + 3'd1;
                end
            end

            // ---- Occupancy update (once for both events) ----
            if (do_push && !do_pop)
                count <= count + 4'd1;
            else if (!do_push && do_pop)
                count <= count - 4'd1;
        end
    end

endmodule