apb-lite-slave-regfile

module TopModule (
    input  wire        clk,
    input  wire        rst,
    input  wire        psel,
    input  wire        penable,
    input  wire        pwrite,
    input  wire [3:0]  paddr,
    input  wire [31:0] pwdata,
    output reg  [31:0] prdata,
    output reg         pready,
    output reg         pslverr
);

    // Writable / storage registers
    reg [31:0] reg0;
    reg [7:0]  reg1_low;
    reg [31:0] reg3;

    // Tracks whether the current word-3 held transaction has already
    // consumed its single wait access cycle.
    reg        w3_waited;

    wire access = psel & penable;

    // -----------------------------------------------------------------
    // Combinational outputs
    // -----------------------------------------------------------------
    always @(*) begin
        prdata  = 32'd0;
        pready  = 1'b0;
        pslverr = 1'b0;

        if (!rst && access) begin
            if (paddr >= 4'd4) begin
                // Off-map: complete with error, no data
                pready  = 1'b1;
                pslverr = 1'b1;
                prdata  = 32'd0;
            end else begin
                // Mapped word
                pslverr = 1'b0;
                if (paddr == 4'd3)
                    pready = w3_waited ? 1'b1 : 1'b0;
                else
                    pready = 1'b1;

                if (!pwrite) begin
                    case (paddr)
                        4'd0: prdata = reg0;
                        4'd1: prdata = {24'd0, reg1_low};
                        4'd2: prdata = 32'h0AB15001;
                        4'd3: prdata = reg3;
                    endcase
                end
            end
        end
    end

    // -----------------------------------------------------------------
    // Sequential: register updates and wait-state tracking
    // -----------------------------------------------------------------
    always @(posedge clk) begin
        if (rst) begin
            reg0      <= 32'd0;
            reg1_low  <= 8'd0;
            reg3      <= 32'd0;
            w3_waited <= 1'b0;
        end else begin
            // Track word-3 wait state
            if (!access)
                w3_waited <= 1'b0;                 // psel or penable fell
            else if (paddr == 4'd3)
                w3_waited <= 1'b1;                 // first access cycle consumed
            else
                w3_waited <= 1'b0;

            // Writes: only on an access cycle where pready=1 and pslverr=0
            if (access && pwrite && (paddr <= 4'd3)) begin
                case (paddr)
                    4'd0: reg0     <= pwdata;
                    4'd1: reg1_low <= pwdata[7:0];
                    4'd2: ;                         // read-only, ignored
                    4'd3: if (w3_waited) reg3 <= pwdata;
                endcase
            end
        end
    end

endmodule