Enable-gated streaming fold stage

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Output:
fold_core/rtl/fold_top.sv
fold_core/rtl/fold_stage.sv
fold_core/rtl/fold_pkg.sv

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sed: can't read rtl/fold_stage.sv: No such file or directory

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Output:
./fold_core/rtl/fold_pkg.sv
./fold_core/rtl/fold_stage.sv
./fold_core/rtl/fold_top.sv

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Output:
//==============================================================================
// fold_stage.sv
//
// Enable-gated streaming fold stage.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and the state registers are provided. The
//  datapath, the phase/priming control and the outputs are left as a TODO and
//  currently drive constant zeros, so the stage produces no useful stream and
//  the verifier FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the
//  module name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module fold_stage #(
    parameter DW    = 12,
    parameter DEPTH = 4,
    parameter NPH   = 8
) (
    input  logic                     clk,
    input  logic                     rst_n,
    input  logic                     en,
    input  logic signed [DW-1:0]     din,
    output logic signed [DW-1:0]     dout,
    output logic                     out_valid
);

  // ---------------------------------------------------------------------------
  // State registers (provided). The head of the feedback line is line[DEPTH-1].
  // ---------------------------------------------------------------------------
  logic signed [DW-1:0] line [0:DEPTH-1];
  logic         [2:0]   phase;
  logic         [2:0]   prime;
  integer               k;

  // ===========================================================================
  // TODO: IMPLEMENT THE STAGE.
  //   * advance every register exactly one step on a rising clk edge with en==1,
  //     and hold all of it when en==0;
  //   * asynchronous active-low reset clears state and outputs;
  //   * drive dout / out_valid per the contract in instruction.md.
  //
  // The placeholder below keeps the module compilable but INCORRECT.
  // ===========================================================================
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      for (k = 0; k < DEPTH; k = k + 1) line[k] <= '0;
      phase <= 3'd0;
      prime <= 3'd0;
    end else begin
      // TODO: replace with the real datapath + control.
      phase <= phase;
      prime <= prime;
    end
  end

  // TODO: replace these placeholder outputs with the real ones.
  assign dout      = '0;
  assign out_valid = 1'b0;

endmodule : fold_stage

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//==============================================================================
// fold_top.sv
//
// Thin integration wrapper. The verification environment drives this wrapper so
// that the instantiation wiring is exercised alongside the stage itself. It
// instantiates fold_stage with the project-default geometry from fold_pkg.
//
// DO NOT change this file.
//==============================================================================
`timescale 1ns/1ps
`include "fold_pkg.sv"

module fold_top (
    input  logic                             clk,
    input  logic                             rst_n,
    input  logic                             en,
    input  logic signed [fold_pkg::DW-1:0]   din,
    output logic signed [fold_pkg::DW-1:0]   dout,
    output logic                             out_valid
);

  // Bare instantiation: the stage carries its own default geometry, so a
  // submission needs no parameter override to elaborate correctly.
  fold_stage u_fold_stage (
      .clk       (clk),
      .rst_n     (rst_n),
      .en        (en),
      .din       (din),
      .dout      (dout),
      .out_valid (out_valid)
  );

endmodule : fold_top

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Output:
//==============================================================================
// fold_pkg.sv
//
// Shared geometry for the enable-gated streaming fold stage. The block carries a
// DEPTH-deep signed feedback line, an eight-step phase counter, and a small
// priming counter. Parameters are declared without an explicit data type for
// broad simulator compatibility (Icarus Verilog 11); they default to integer
// constants, which is sufficient here.
//
// DO NOT change this file.
//==============================================================================
`ifndef FOLD_PKG_SV
`define FOLD_PKG_SV

package fold_pkg;

  localparam DW    = 12;   // sample word width (signed two's complement)
  localparam DEPTH = 4;    // feedback line depth (= load/combine window length)
  localparam NPH   = 8;    // phase counter span: 0..3 load window, 4..7 combine

endpackage : fold_pkg

`endif // FOLD_PKG_SV

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Output:
fold_core/rtl/fold_pkg.sv
fold_core/rtl/fold_stage.sv
fold_core/rtl/fold_top.sv

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Output:
fold_core/rtl/fold_stage.sv:47: syntax error
fold_core/rtl/fold_stage.sv:46: error: Syntax error defining function.
fold_core/rtl/fold_stage.sv:66: syntax error
fold_core/rtl/fold_stage.sv:65: error: Syntax error defining function.

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Output:
/bin/bash: line 1: git: command not found

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Output:
    35	    output logic                     out_valid
    36	);
    37	
    38	  // ---------------------------------------------------------------------------
    39	  // State registers (provided). The head of the feedback line is line[DEPTH-1].
    40	  // ---------------------------------------------------------------------------
    41	  logic signed [DW-1:0] line [0:DEPTH-1];
    42	  logic         [2:0]   phase;
    43	  logic         [2:0]   prime;
    44	  integer               k;
    45	
    46	  function automatic logic signed [DW-1:0] round_half_up;
    47	    input logic signed [DW-1:0] a;
    48	    input logic signed [DW-1:0] b;
    49	
    50	    logic signed [DW:0] a_ext;
    51	    logic signed [DW:0] b_ext;
    52	    logic signed [DW:0] one_ext;
    53	    logic signed [DW:0] sum_ext;
    54	    logic signed [DW:0] round_ext;
    55	    begin
    56	      a_ext = a;
    57	      b_ext = b;
    58	      one_ext = {{DW{1'b0}}, 1'b1};
    59	      sum_ext = a_ext + b_ext + one_ext;
    60	      round_ext = sum_ext >>> 1;
    61	      round_half_up = round_ext[DW-1:0];
    62	    end
    63	  endfunction
    64	
    65	  function automatic logic signed [DW-1:0] sat_sub;
    66	    input logic signed [DW-1:0] a;
    67	    input logic signed [DW-1:0] b;
    68	
    69	    logic signed [DW:0] a_ext;
    70	    logic signed [DW:0] b_ext;
    71	    logic signed [DW:0] diff_ext;
    72	    logic signed [DW:0] max_ext;
    73	    logic signed [DW:0] min_ext;
    74	    begin
    75	      a_ext = a;
    76	      b_ext = b;
    77	      diff_ext = a_ext - b_ext;
    78	      max_ext = {2'b00, {(DW-1){1'b1}}};
    79	      min_ext = {2'b11, {(DW-1){1'b0}}};
    80	
    81	      if (diff_ext > max_ext) begin
    82	        sat_sub = {1'b0, {(DW-1){1'b1}}};
    83	      end else if (diff_ext < min_ext) begin
    84	        sat_sub = {1'b1, {(DW-1){1'b0}}};
    85	      end else begin

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Output:
/tmp/fold_stage_tb.sv:67: syntax error

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Output:
     1	//==============================================================================
     2	// fold_stage.sv
     3	//
     4	// Enable-gated streaming fold stage.
     5	//
     6	// ---------------------------------------------------------------------------
     7	//  >>> IMPLEMENTATION REQUIRED <<<
     8	//
     9	//  The module ports, parameters and the state registers are provided. The
    10	//  datapath, the phase/priming control and the outputs are left as a TODO and
    11	//  currently drive constant zeros, so the stage produces no useful stream and
    12	//  the verifier FAILS.
    13	//
    14	//  Implement the behaviour described in instruction.md. Do NOT change the
    15	//  module name, the port list, or the parameter list.
    16	//
    17	//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
    18	//  function-call result) is a syntax error under `iverilog -g2012`. Index only
    19	//  named signals, and do any bit work that needs an intermediate value inside a
    20	//  `function automatic` using named locals.
    21	// ---------------------------------------------------------------------------
    22	//==============================================================================
    23	`timescale 1ns/1ps
    24	
    25	module fold_stage #(
    26	    parameter DW    = 12,
    27	    parameter DEPTH = 4,
    28	    parameter NPH   = 8
    29	) (
    30	    input  logic                     clk,
    31	    input  logic                     rst_n,
    32	    input  logic                     en,
    33	    input  logic signed [DW-1:0]     din,
    34	    output logic signed [DW-1:0]     dout,
    35	    output logic                     out_valid
    36	);
    37	
    38	  // ---------------------------------------------------------------------------
    39	  // State registers (provided). The head of the feedback line is line[DEPTH-1].
    40	  // ---------------------------------------------------------------------------
    41	  logic signed [DW-1:0] line [0:DEPTH-1];
    42	  logic         [2:0]   phase;
    43	  logic         [2:0]   prime;
    44	  integer               k;
    45	
    46	  function automatic signed [DW-1:0] round_half_up;
    47	    input signed [DW-1:0] a;
    48	    input signed [DW-1:0] b;
    49	
    50	    reg signed [DW:0] a_ext;
    51	    reg signed [DW:0] b_ext;
    52	    reg signed [DW:0] one_ext;
    53	    reg signed [DW:0] sum_ext;
    54	    reg signed [DW:0] round_ext;
    55	    begin
    56	      a_ext = a;
    57	      b_ext = b;
    58	      one_ext = {{DW{1'b0}}, 1'b1};
    59	      sum_ext = a_ext + b_ext + one_ext;
    60	      round_ext = sum_ext >>> 1;
    61	      round_half_up = round_ext[DW-1:0];
    62	    end
    63	  endfunction
    64	
    65	  function automatic signed [DW-1:0] sat_sub;
    66	    input signed [DW-1:0] a;
    67	    input signed [DW-1:0] b;
    68	
    69	    reg signed [DW:0] a_ext;
    70	    reg signed [DW:0] b_ext;
    71	    reg signed [DW:0] diff_ext;
    72	    reg signed [DW:0] max_ext;
    73	    reg signed [DW:0] min_ext;
    74	    begin
    75	      a_ext = a;
    76	      b_ext = b;
    77	      diff_ext = a_ext - b_ext;
    78	      max_ext = {2'b00, {(DW-1){1'b1}}};
    79	      min_ext = {2'b11, {(DW-1){1'b0}}};
    80	
    81	      if (diff_ext > max_ext) begin
    82	        sat_sub = {1'b0, {(DW-1){1'b1}}};
    83	      end else if (diff_ext < min_ext) begin
    84	        sat_sub = {1'b1, {(DW-1){1'b0}}};
    85	      end else begin
    86	        sat_sub = diff_ext[DW-1:0];
    87	      end
    88	    end
    89	  endfunction
    90	
    91	  always_ff @(posedge clk or negedge rst_n) begin
    92	    if (!rst_n) begin
    93	      for (k = 0; k < DEPTH; k = k + 1) line[k] <= '0;
    94	      phase <= 3'd0;
    95	      prime <= 3'd0;
    96	      dout <= '0;
    97	      out_valid <= 1'b0;
    98	    end else begin
    99	      if (en) begin
   100	        if (phase < DEPTH[2:0]) begin
   101	          dout <= line[DEPTH-1];
   102	          line[0] <= din;
   103	        end else begin
   104	          dout <= round_half_up(line[DEPTH-1], din);
   105	          line[0] <= sat_sub(line[DEPTH-1], din);
   106	        end
   107	
   108	        for (k = 1; k < DEPTH; k = k + 1) line[k] <= line[k-1];
   109	
   110	        if (phase == (NPH-1)) begin
   111	          phase <= 3'd0;
   112	        end else begin
   113	          phase <= phase + 3'd1;
   114	        end
   115	
   116	        if (prime < DEPTH[2:0]) begin
   117	          prime <= prime + 3'd1;
   118	        end
   119	
   120	        out_valid <= (prime >= DEPTH[2:0]);
   121	      end
   122	    end
   123	  end
   124	
   125	endmodule : fold_stage

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    58	      ref_phase = 3'd0;
    59	      ref_prime = 3'd0;
    60	      exp_dout = '0;
    61	      exp_valid = 1'b0;
    62	      accepted = 0;
    63	    end
    64	  endtask
    65	
    66	  task automatic step;
    67	    input logic step_en;
    68	    input logic signed [11:0] step_din;
    69	    reg signed [11:0] insert_val;
    70	    begin
    71	      en = step_en;
    72	      din = step_din;
    73	      @(posedge clk);
    74	      #1;
    75	
    76	      if (step_en) begin

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PASS

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Output:
  // ---------------------------------------------------------------------------
  logic signed [DW-1:0] line [0:DEPTH-1];
  logic         [2:0]   phase;
  logic         [2:0]   prime;
  integer               k;

  function automatic signed [DW-1:0] round_half_up;
    input signed [DW-1:0] a;
    input signed [DW-1:0] b;

    reg signed [DW:0] a_ext;
    reg signed [DW:0] b_ext;
    reg signed [DW:0] one_ext;
    reg signed [DW:0] sum_ext;
    reg signed [DW:0] round_ext;
    begin
      a_ext = a;
      b_ext = b;
      one_ext = {{DW{1'b0}}, 1'b1};
      sum_ext = a_ext + b_ext + one_ext;
      round_ext = sum_ext >>> 1;
      round_half_up = round_ext[DW-1:0];
    end
  endfunction

  function automatic signed [DW-1:0] sat_sub;
    input signed [DW-1:0] a;
    input signed [DW-1:0] b;

    reg signed [DW:0] a_ext;
    reg signed [DW:0] b_ext;
    reg signed [DW:0] diff_ext;
    reg signed [DW:0] max_ext;
    reg signed [DW:0] min_ext;
    begin
      a_ext = a;
      b_ext = b;
      diff_ext = a_ext - b_ext;
      max_ext = {2'b00, {(DW-1){1'b1}}};
      min_ext = {2'b11, {(DW-1){1'b0}}};

      if (diff_ext > max_ext) begin
        sat_sub = {1'b0, {(DW-1){1'b1}}};
      end else if (diff_ext < min_ext) begin
        sat_sub = {1'b1, {(DW-1){1'b0}}};
      end else begin
        sat_sub = diff_ext[DW-1:0];
      end
    end
  endfunction

  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      for (k = 0; k < DEPTH; k = k + 1) line[k] <= '0;
      phase <= 3'd0;
      prime <= 3'd0;
      dout <= '0;
      out_valid <= 1'b0;
    end else begin
      if (en) begin
        if (phase < DEPTH[2:0]) begin
          dout <= line[DEPTH-1];
          line[0] <= din;
        end else begin
          dout <= round_half_up(line[DEPTH-1], din);
          line[0] <= sat_sub(line[DEPTH-1], din);
        end

        for (k = 1; k < DEPTH; k = k + 1) line[k] <= line[k-1];

        if (phase == (NPH-1)) begin
          phase <= 3'd0;
        end else begin
          phase <= phase + 3'd1;
        end

        if (prime < DEPTH[2:0]) begin
          prime <= prime + 3'd1;
        end

        out_valid <= (prime >= DEPTH[2:0]);
      end
    end
  end

endmodule : fold_stage