byte-serial-round-scheduler

module TopModule (
    input              clk,
    input              rst_n,
    input              start,
    input      [127:0] block_in,
    input      [127:0] round_key0,
    input      [3:0]   num_rounds,
    input              reseed,
    input      [3:0]   reseed_round,
    output reg         ready,
    output reg         result_valid,
    output reg [127:0] block_out
);

    reg [127:0] state;
    reg [127:0] key_reg;
    reg [3:0]   num_rounds_reg;
    reg [3:0]   round_index;
    reg [7:0]   start_fb;
    reg         busy;
    reg [127:0] ns;

    // Compute one full round: 16 byte slots (columns 0..3, high byte first)
    // then the key-mix slot. Each byte slot: state[p] = rol1(state[p] ^ fb) ^ 0x63,
    // with fb = start feedback for slot 0, else the previous slot's (new) byte.
    function [127:0] do_round;
        input [127:0] s_in;
        input [7:0]   fb0;
        input [127:0] k;
        reg   [127:0] s;
        reg   [7:0]   f;
        reg   [3:0]   p;
        reg   [7:0]   b, t, nb;
        integer j, c, kk;
        begin
            s = s_in;
            f = fb0;
            for (j = 0; j < 16; j = j + 1) begin
                c  = j / 4;                 // column 0..3
                kk = j % 4;                 // byte within column: 0->[31:24] .. 3->[7:0]
                p  = 4*c + (3 - kk);        // byte index into state
                b  = s[8*p +: 8];
                t  = b ^ f;
                nb = {t[6:0], t[7]} ^ 8'h63; // rol1(b ^ fb) ^ 0x63
                s[8*p +: 8] = nb;
                f  = nb;
            end
            do_round = s ^ k;               // key-mix slot
        end
    endfunction

    always @(posedge clk) begin
        if (!rst_n) begin
            ready        <= 1'b1;
            result_valid <= 1'b0;
            busy         <= 1'b0;
        end else begin
            result_valid <= 1'b0;
            if (busy) begin
                ns = do_round(state, start_fb, key_reg);
                if ((round_index + 4'd1) == num_rounds_reg) begin
                    // finishing key-mix slot of the last round
                    block_out    <= ns;
                    result_valid <= 1'b1;
                    ready        <= 1'b1;
                    busy         <= 1'b0;
                end else begin
                    state       <= ns;
                    round_index <= round_index + 4'd1;
                    // Fix next round's start feedback at this key-mix slot.
                    start_fb    <= reseed ? {4'b0, reseed_round}
                                          : {4'b0, (round_index + 4'd1)};
                    ready       <= 1'b0;
                end
            end else if (ready && start) begin
                // Load a new operation.
                state          <= block_in;
                key_reg        <= round_key0;
                num_rounds_reg <= num_rounds;
                round_index    <= 4'b0;
                start_fb       <= 8'b0;      // round 0 feedback = {4'b0, round_index=0}
                busy           <= 1'b1;
                ready          <= 1'b0;
            end
        end
    end

endmodule