Serial bit-destuff framer

Chunk ID: e302d5
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Output:
/work/bds_core/rtl/bds.sv
/work/bds_core/rtl/bds_pkg.sv
/work/bds_core/rtl/bds_top.sv

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//==============================================================================
// bds.sv
//
// Serial bit-destuff framer.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and the run-count register are provided. The
//  destuff / flag / abort decode and the outputs are left as a TODO and
//  currently drive constant zeros, so the block emits nothing and the verifier
//  FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the module
//  name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals. Keep the run count in a named
//  register.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module bds #(
    parameter RUN_W   = 3,
    parameter STUFF_R = 5,
    parameter FLAG_R  = 6,
    parameter ABORT_R = 6
) (
    input  logic clk,
    input  logic rst_n,
    input  logic s_in,
    input  logic s_valid,
    output logic d_out,
    output logic d_valid,
    output logic flag,
    output logic abort
);

  // ---------------------------------------------------------------------------
  // State (provided): running count of consecutive 1 bits seen on the input
  // stream, BEFORE the bit currently being processed.
  // ---------------------------------------------------------------------------
  logic [RUN_W-1:0] run;

  // ===========================================================================
  // TODO: IMPLEMENT THE FRAMER.
  //   * process s_in only on cycles where s_valid is high; freeze every register
  //     (the run count and the outputs) on a stall;
  //   * maintain the consecutive-1 run count and use it to remove stuffed bits,
  //     detect flags, and detect aborts;
  //   * drive d_out / d_valid / flag / abort per the contract in instruction.md;
  //   * asynchronous active-low reset clears the run count and all outputs.
  //
  // The placeholder below keeps the module compilable but INCORRECT.
  // ===========================================================================
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      run <= '0;
    end else begin
      // TODO: replace with the real decode + control.
      run <= run;
    end
  end

  // TODO: replace these placeholder outputs with the real ones.
  assign d_out   = 1'b0;
  assign d_valid = 1'b0;
  assign flag    = 1'b0;
  assign abort   = 1'b0;

endmodule : bds

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Output:
//==============================================================================
// bds_pkg.sv
//
// Shared constants for the serial bit-destuff framer. The receiver keeps a small
// running count of consecutive 1 bits seen on the input stream; that one count
// drives stuff-bit removal, flag detection, abort detection and the output
// strobe together. The threshold constants live here so the data path and the
// integration wrapper agree on the geometry.
//
// Parameters are declared without an explicit data type for broad simulator
// compatibility (Icarus Verilog 11); they default to plain integer constants,
// which is sufficient here.
//
// DO NOT change this file.
//==============================================================================
`ifndef BDS_PKG_SV
`define BDS_PKG_SV

package bds_pkg;

  // Width of the consecutive-1 run counter. It only ever needs to represent the
  // values 0..6 (a seventh consecutive 1 is consumed as an abort and resets the
  // count), so three bits is ample.
  localparam RUN_W   = 3;

  // Run-length landmarks the contract keys off (counts of consecutive 1 bits
  // already seen, i.e. the run value BEFORE the bit currently being processed).
  localparam STUFF_R = 5;   // a 0 seen with exactly this many 1s before it is a stuffed bit
  localparam FLAG_R  = 6;   // a 0 seen with exactly this many 1s before it closes a flag
  localparam ABORT_R = 6;   // a 1 seen with this many 1s before it is the seventh 1 -> abort

endpackage : bds_pkg

`endif // BDS_PKG_SV

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//==============================================================================
// bds_top.sv
//
// Thin integration wrapper. The verification environment drives this wrapper so
// that the instantiation wiring is exercised alongside the destuff framer
// itself. It instantiates bds with the project-default geometry from bds_pkg.
//
// DO NOT change this file.
//==============================================================================
`timescale 1ns/1ps
`include "bds_pkg.sv"

module bds_top (
    input  logic clk,
    input  logic rst_n,
    input  logic s_in,
    input  logic s_valid,
    output logic d_out,
    output logic d_valid,
    output logic flag,
    output logic abort
);

  // Bare instantiation: the framer carries its own default geometry, so a
  // submission needs no parameter override to elaborate correctly.
  bds u_bds (
      .clk     (clk),
      .rst_n   (rst_n),
      .s_in    (s_in),
      .s_valid (s_valid),
      .d_out   (d_out),
      .d_valid (d_valid),
      .flag    (flag),
      .abort   (abort)
  );

endmodule : bds_top

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rtl/bds_top.sv:12: Include file bds_pkg.sv not found

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PASS

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Output:
/bin/bash: line 1: git: command not found

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Output:
/bin/bash: line 1: git: command not found

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Output:
//==============================================================================
// bds.sv
//
// Serial bit-destuff framer.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and the run-count register are provided. The
//  destuff / flag / abort decode and the outputs are left as a TODO and
//  currently drive constant zeros, so the block emits nothing and the verifier
//  FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the module
//  name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals. Keep the run count in a named
//  register.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module bds #(
    parameter RUN_W   = 3,
    parameter STUFF_R = 5,
    parameter FLAG_R  = 6,
    parameter ABORT_R = 6
) (
    input  logic clk,
    input  logic rst_n,
    input  logic s_in,
    input  logic s_valid,
    output logic d_out,
    output logic d_valid,
    output logic flag,
    output logic abort
);

  // ---------------------------------------------------------------------------
  // State (provided): running count of consecutive 1 bits seen on the input
  // stream, BEFORE the bit currently being processed.
  // ---------------------------------------------------------------------------
  logic [RUN_W-1:0] run;

  // ===========================================================================
  // Destuff / flag / abort decode.
  // ===========================================================================
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      run     <= '0;
      d_out   <= 1'b0;
      d_valid <= 1'b0;
      flag    <= 1'b0;
      abort   <= 1'b0;
    end else begin
      d_valid <= 1'b0;
      flag    <= 1'b0;
      abort   <= 1'b0;

      if (s_valid) begin
        if (s_in) begin
          if (run == ABORT_R[RUN_W-1:0]) begin
            abort <= 1'b1;
            run   <= '0;
          end else begin
            d_out   <= 1'b1;
            d_valid <= 1'b1;
            run     <= run + {{(RUN_W-1){1'b0}}, 1'b1};
          end
        end else begin
          if (run == STUFF_R[RUN_W-1:0]) begin
            run <= '0;
          end else if (run == FLAG_R[RUN_W-1:0]) begin
            flag <= 1'b1;
            run  <= '0;
          end else begin
            d_out   <= 1'b0;
            d_valid <= 1'b1;
            run     <= '0;
          end
        end
      end
    end
  end

endmodule : bds

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