coprocessor-dispatcher-classmix

module TopModule (
    input             clk,
    input             rst,
    input             op_valid_i,
    input      [1:0]  op_class_i,
    input      [1:0]  op_rd_i,
    input      [15:0] op_data_i,
    input             c2_done_i,
    output            op_accept_o,
    output            wb_valid_o,
    output     [1:0]  wb_rd_o,
    output     [15:0] wb_data_o,
    output            c2_busy_o,
    output reg [3:0]  inflight_o
);

    // ---- Slot state (one slot per class 0,1,2) ----
    reg        occ0, occ1, occ2;   // slot occupied
    reg [1:0]  rd0, rd1, rd2;     // destination register
    reg [15:0] dat0, dat1, dat2;    // pending writeback data
    reg        r1;                  // class1: matured (two cycles after accept)
    reg        r2;                  // class2: ready (sticky once c2 done)

    // ---- Combinational accept ----
    wire slot_empty = (op_class_i == 2'd0) ? ~occ0 :
                      (op_class_i == 2'd1) ? ~occ1 :
                      (op_class_i == 2'd2) ? ~occ2 : 1'b0; // class 3 never accepted

    wire accept = !rst && op_valid_i && (op_class_i != 2'd3) &&
                  !inflight_o[op_rd_i] && slot_empty;

    assign op_accept_o = accept;
    assign c2_busy_o   = occ2;

    // ---- Writeback eligibility (from registered state) ----
    wire fire0 = occ0;          // class0 ready one cycle after accept
    wire fire1 = occ1 & r1;     // class1 ready two cycles after accept
    wire fire2 = occ2 & r2;     // class2 ready once c2_done seen while busy

    // Priority: class 0, then 1, then 2. Only one writeback per cycle.
    assign wb_valid_o = !rst & (fire0 | fire1 | fire2);
    assign wb_rd_o    = fire0 ? rd0  : fire1 ? rd1  : rd2;
    assign wb_data_o  = fire0 ? dat0 : fire1 ? dat1 : dat2;

    always @(posedge clk) begin
        if (rst) begin
            occ0 <= 1'b0; occ1 <= 1'b0; occ2 <= 1'b0;
            r1   <= 1'b0; r2   <= 1'b0;
            inflight_o <= 4'b0;
        end else begin
            // class1 matures the cycle after it becomes occupied
            if (occ1)
                r1 <= 1'b1;
            // class2 becomes ready (sticky) when c2_done_i high at an edge while busy
            if (occ2 & c2_done_i)
                r2 <= 1'b1;

            // Perform the single selected writeback: free slot, clear inflight bit
            if (fire0) begin
                occ0 <= 1'b0;
                inflight_o[rd0] <= 1'b0;
            end else if (fire1) begin
                occ1 <= 1'b0;
                r1   <= 1'b0;
                inflight_o[rd1] <= 1'b0;
            end else if (fire2) begin
                occ2 <= 1'b0;
                r2   <= 1'b0;
                inflight_o[rd2] <= 1'b0;
            end

            // Accept a new request: store and set its destination bit
            if (accept) begin
                inflight_o[op_rd_i] <= 1'b1;
                case (op_class_i)
                    2'd0: begin
                        occ0 <= 1'b1;
                        rd0  <= op_rd_i;
                        dat0 <= op_data_i + 16'd1;
                    end
                    2'd1: begin
                        occ1 <= 1'b1;
                        r1   <= 1'b0;
                        rd1  <= op_rd_i;
                        dat1 <= op_data_i << 1;
                    end
                    2'd2: begin
                        occ2 <= 1'b1;
                        r2   <= 1'b0;
                        rd2  <= op_rd_i;
                        dat2 <= op_data_i ^ 16'hffff;
                    end
                    default: ; // class 3 never stored
                endcase
            end
        end
    end

endmodule