Resynchronising serial byte receiver

Chunk ID: 65c232
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Output:
srx_core/rtl/srx_top.sv
srx_core/rtl/srx_pkg.sv
srx_core/rtl/srx.sv

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Output:
/bin/bash: line 1: git: command not found

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Output:
//==============================================================================
// srx.sv
//
// Asynchronous serial byte receiver for a line that idles high.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and a set of state registers are provided. The
//  frame FSM, the bit-period counter, the sampling datapath and the outputs are
//  left as a TODO and currently drive constant zeros, so the receiver produces
//  no useful result and the verifier FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the
//  module name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module srx #(
    parameter BITLEN = 16,
    parameter DW     = 8
) (
    input  logic               clk,
    input  logic               rst_n,    // asynchronous, active low
    input  logic               rx,       // serial input, idles high
    input  logic               take,     // downstream-consumed strobe
    output logic [DW-1:0]      data,      // received byte (level held)
    output logic               valid,     // 1-cycle good-frame strobe
    output logic               frame_err, // 1-cycle framing-error strobe
    output logic               busy        // high from confirmed start to result
);

  // ---------------------------------------------------------------------------
  // State registers (provided). You may add more if your design needs them.
  // ---------------------------------------------------------------------------
  logic [1:0]      state;      // frame FSM state
  integer          cnt;        // bit-period down-counter
  integer          bit_idx;    // which bit is being sampled
  logic [DW-1:0]   shifter;    // assembling byte
  integer          hi_run;     // line-idle (high-run) counter

  // ===========================================================================
  // TODO: IMPLEMENT THE RECEIVER.
  //   * qualify a start, sample the data bits, drive valid/frame_err/data/busy
  //     and run the post-error resync window per the contract in instruction.md;
  //   * asynchronous active-low reset clears all state and outputs.
  //
  // The placeholder below keeps the module compilable but INCORRECT.
  // ===========================================================================
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      state     <= 2'd0;
      cnt       <= 0;
      bit_idx   <= 0;
      shifter   <= {DW{1'b0}};
      hi_run    <= 0;
    end else begin
      // TODO: replace with the real FSM + datapath.
      state   <= state;
      cnt     <= cnt;
      bit_idx <= bit_idx;
      shifter <= shifter;
      hi_run  <= hi_run;
    end
  end

  // TODO: replace these placeholder outputs with the real ones.
  assign data      = {DW{1'b0}};
  assign valid     = 1'b0;
  assign frame_err = 1'b0;
  assign busy      = 1'b0;

endmodule : srx

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Output:
//==============================================================================
// srx_pkg.sv
//
// Shared geometry for the asynchronous serial byte receiver. The block carries
// one bit-period counter, a small frame FSM, an LSB-first shift register and a
// resync high-run counter. Parameters are declared without an explicit data
// type for broad simulator compatibility (Icarus Verilog 11); they default to
// integer constants, which is sufficient here.
//
// DO NOT change this file.
//==============================================================================
`ifndef SRX_PKG_SV
`define SRX_PKG_SV

package srx_pkg;

  localparam BITLEN = 16;   // bit period in clk cycles (>= 8, even)
  localparam DW     = 8;    // data word width (one serial byte)

endpackage : srx_pkg

`endif // SRX_PKG_SV

Chunk ID: 3930ba
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Output:
//==============================================================================
// srx_top.sv
//
// Thin integration wrapper. The verification environment drives this wrapper so
// the instantiation wiring is exercised alongside the receiver itself. It
// instantiates srx with the project-default geometry from srx_pkg.
//
// DO NOT change this file.
//==============================================================================
`timescale 1ns/1ps
`include "srx_pkg.sv"

module srx_top (
    input  logic                       clk,
    input  logic                       rst_n,
    input  logic                       rx,
    input  logic                       take,
    output logic [srx_pkg::DW-1:0]     data,
    output logic                       valid,
    output logic                       frame_err,
    output logic                       busy
);

  // Bare instantiation: the receiver carries its own default geometry, so a
  // submission needs no parameter override to elaborate correctly.
  srx u_srx (
      .clk       (clk),
      .rst_n     (rst_n),
      .rx        (rx),
      .take      (take),
      .data      (data),
      .valid     (valid),
      .frame_err (frame_err),
      .busy      (busy)
  );

endmodule : srx_top

Chunk ID: 9c1f18
Wall time: 0.0000 seconds
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Original token count: 12
Output:
./rtl/srx.sv
./rtl/srx_pkg.sv
./rtl/srx_top.sv

Chunk ID: 12c0a4
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 58
Output:
warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- package srx_pkg declared here: rtl/srx_pkg.sv:15

Chunk ID: 77f14d
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Original token count: 1392
Output:
//==============================================================================
// srx.sv
//
// Asynchronous serial byte receiver for a line that idles high.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and a set of state registers are provided. The
//  frame FSM, the bit-period counter, the sampling datapath and the outputs are
//  left as a TODO and currently drive constant zeros, so the receiver produces
//  no useful result and the verifier FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the
//  module name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module srx #(
    parameter BITLEN = 16,
    parameter DW     = 8
) (
    input  logic               clk,
    input  logic               rst_n,    // asynchronous, active low
    input  logic               rx,       // serial input, idles high
    input  logic               take,     // downstream-consumed strobe
    output logic [DW-1:0]      data,      // received byte (level held)
    output logic               valid,     // 1-cycle good-frame strobe
    output logic               frame_err, // 1-cycle framing-error strobe
    output logic               busy        // high from confirmed start to result
);

  // ---------------------------------------------------------------------------
  // State registers (provided). You may add more if your design needs them.
  // ---------------------------------------------------------------------------
  logic [1:0]      state;      // frame FSM state
  integer          cnt;        // bit-period down-counter
  integer          bit_idx;    // which bit is being sampled
  logic [DW-1:0]   shifter;    // assembling byte
  integer          hi_run;     // line-idle (high-run) counter
  logic            rx_d;       // previous sampled rx value for edge detection

  localparam [1:0] ST_IDLE   = 2'd0;
  localparam [1:0] ST_START  = 2'd1;
  localparam [1:0] ST_DATA   = 2'd2;
  localparam [1:0] ST_RESYNC = 2'd3;

  localparam integer START_WAIT = (BITLEN / 2) - 1;
  localparam integer BIT_WAIT   = BITLEN - 1;

  // ===========================================================================
  // TODO: IMPLEMENT THE RECEIVER.
  //   * qualify a start, sample the data bits, drive valid/frame_err/data/busy
  //     and run the post-error resync window per the contract in instruction.md;
  //   * asynchronous active-low reset clears all state and outputs.
  //
  // The placeholder below keeps the module compilable but INCORRECT.
  // ===========================================================================
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      state     <= ST_IDLE;
      cnt       <= 0;
      bit_idx   <= 0;
      shifter   <= {DW{1'b0}};
      hi_run    <= 0;
      rx_d      <= 1'b1;
      data      <= {DW{1'b0}};
      valid     <= 1'b0;
      frame_err <= 1'b0;
      busy      <= 1'b0;
    end else begin
      rx_d      <= rx;
      valid     <= 1'b0;
      frame_err <= 1'b0;

      case (state)
        ST_IDLE: begin
          busy   <= 1'b0;
          hi_run <= 0;

          if (rx_d && !rx) begin
            state <= ST_START;
            cnt   <= START_WAIT;
          end
        end

        ST_START: begin
          busy <= 1'b0;

          if (cnt == 0) begin
            if (!rx) begin
              state   <= ST_DATA;
              cnt     <= BIT_WAIT;
              bit_idx <= 0;
              shifter <= {DW{1'b0}};
              busy    <= 1'b1;
            end else begin
              state <= ST_IDLE;
            end
          end else begin
            cnt <= cnt - 1;
          end
        end

        ST_DATA: begin
          busy <= 1'b1;

          if (cnt == 0) begin
            if (bit_idx < DW) begin
              shifter[bit_idx] <= rx;
              cnt <= BIT_WAIT;

              if (bit_idx == (DW - 1)) begin
                bit_idx <= DW;
              end else begin
                bit_idx <= bit_idx + 1;
              end
            end else begin
              if (rx) begin
                data  <= shifter;
                valid <= 1'b1;
                state <= ST_IDLE;
              end else begin
                frame_err <= 1'b1;
                state     <= ST_RESYNC;
                hi_run    <= 0;
              end

              busy <= 1'b1;
            end
          end else begin
            cnt <= cnt - 1;
          end
        end

        ST_RESYNC: begin
          busy <= 1'b0;

          if (rx) begin
            if (hi_run >= (BITLEN - 1)) begin
              state  <= ST_IDLE;
              hi_run <= BITLEN;
            end else begin
              hi_run <= hi_run + 1;
            end
          end else begin
            hi_run <= 0;
          end
        end

        default: begin
          state   <= ST_IDLE;
          cnt     <= 0;
          bit_idx <= 0;
          shifter <= {DW{1'b0}};
          hi_run  <= 0;
          busy    <= 1'b0;
        end
      endcase
    end
  end

endmodule : srx

Chunk ID: e955eb
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Output:
PASS

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Output:

Chunk ID: 23ccb3
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Output:
warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- package srx_pkg declared here: rtl/srx_pkg.sv:15

Chunk ID: d1d268
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 12
Output:
./rtl/srx.sv
./rtl/srx_pkg.sv
./rtl/srx_top.sv

Chunk ID: d14f2d
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 1415
Output:
     1	//==============================================================================
     2	// srx.sv
     3	//
     4	// Asynchronous serial byte receiver for a line that idles high.
     5	//
     6	// ---------------------------------------------------------------------------
     7	//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
     8	//  function-call result) is a syntax error under `iverilog -g2012`. Index only
     9	//  named signals, and do any bit work that needs an intermediate value inside a
    10	//  `function automatic` using named locals.
    11	// ---------------------------------------------------------------------------
    12	//==============================================================================
    13	`timescale 1ns/1ps
    14	
    15	module srx #(
    16	    parameter BITLEN = 16,
    17	    parameter DW     = 8
    18	) (
    19	    input  logic               clk,
    20	    input  logic               rst_n,    // asynchronous, active low
    21	    input  logic               rx,       // serial input, idles high
    22	    input  logic               take,     // downstream-consumed strobe
    23	    output logic [DW-1:0]      data,      // received byte (level held)
    24	    output logic               valid,     // 1-cycle good-frame strobe
    25	    output logic               frame_err, // 1-cycle framing-error strobe
    26	    output logic               busy        // high from confirmed start to result
    27	);
    28	
    29	  // ---------------------------------------------------------------------------
    30	  // State registers (provided). You may add more if your design needs them.
    31	  // ---------------------------------------------------------------------------
    32	  logic [1:0]      state;      // frame FSM state
    33	  integer          cnt;        // bit-period down-counter
    34	  integer          bit_idx;    // which bit is being sampled
    35	  logic [DW-1:0]   shifter;    // assembling byte
    36	  integer          hi_run;     // line-idle (high-run) counter
    37	  logic            rx_d;       // previous sampled rx value for edge detection
    38	
    39	  localparam [1:0] ST_IDLE   = 2'd0;
    40	  localparam [1:0] ST_START  = 2'd1;
    41	  localparam [1:0] ST_DATA   = 2'd2;
    42	  localparam [1:0] ST_RESYNC = 2'd3;
    43	
    44	  localparam integer START_WAIT = (BITLEN / 2) - 1;
    45	  localparam integer BIT_WAIT   = BITLEN - 1;
    46	
    47	  always_ff @(posedge clk or negedge rst_n) begin
    48	    if (!rst_n) begin
    49	      state     <= ST_IDLE;
    50	      cnt       <= 0;
    51	      bit_idx   <= 0;
    52	      shifter   <= {DW{1'b0}};
    53	      hi_run    <= 0;
    54	      rx_d      <= 1'b1;
    55	      data      <= {DW{1'b0}};
    56	      valid     <= 1'b0;
    57	      frame_err <= 1'b0;
    58	      busy      <= 1'b0;
    59	    end else begin
    60	      rx_d      <= rx;
    61	      valid     <= 1'b0;
    62	      frame_err <= 1'b0;
    63	
    64	      case (state)
    65	        ST_IDLE: begin
    66	          busy   <= 1'b0;
    67	          hi_run <= 0;
    68	
    69	          if (rx_d && !rx) begin
    70	            state <= ST_START;
    71	            cnt   <= START_WAIT;
    72	          end
    73	        end
    74	
    75	        ST_START: begin
    76	          busy <= 1'b0;
    77	
    78	          if (cnt == 0) begin
    79	            if (!rx) begin
    80	              state   <= ST_DATA;
    81	              cnt     <= BIT_WAIT;
    82	              bit_idx <= 0;
    83	              shifter <= {DW{1'b0}};
    84	              busy    <= 1'b1;
    85	            end else begin
    86	              state <= ST_IDLE;
    87	            end
    88	          end else begin
    89	            cnt <= cnt - 1;
    90	          end
    91	        end
    92	
    93	        ST_DATA: begin
    94	          busy <= 1'b1;
    95	
    96	          if (cnt == 0) begin
    97	            if (bit_idx < DW) begin
    98	              shifter[bit_idx] <= rx;
    99	              cnt <= BIT_WAIT;
   100	
   101	              if (bit_idx == (DW - 1)) begin
   102	                bit_idx <= DW;
   103	              end else begin
   104	                bit_idx <= bit_idx + 1;
   105	              end
   106	            end else begin
   107	              if (rx) begin
   108	                data  <= shifter;
   109	                valid <= 1'b1;
   110	                state <= ST_IDLE;
   111	              end else begin
   112	                frame_err <= 1'b1;
   113	                state     <= ST_RESYNC;
   114	                hi_run    <= 0;
   115	              end
   116	
   117	              busy <= 1'b1;
   118	            end
   119	          end else begin
   120	            cnt <= cnt - 1;
   121	          end
   122	        end
   123	
   124	        ST_RESYNC: begin
   125	          busy <= 1'b0;
   126	
   127	          if (rx) begin
   128	            if (hi_run >= (BITLEN - 1)) begin
   129	              state  <= ST_IDLE;
   130	              hi_run <= BITLEN;
   131	            end else begin
   132	              hi_run <= hi_run + 1;
   133	            end
   134	          end else begin
   135	            hi_run <= 0;
   136	          end
   137	        end
   138	
   139	        default: begin
   140	          state   <= ST_IDLE;
   141	          cnt     <= 0;
   142	          bit_idx <= 0;
   143	          shifter <= {DW{1'b0}};
   144	          hi_run  <= 0;
   145	          busy    <= 1'b0;
   146	        end
   147	      endcase
   148	    end
   149	  end
   150	
   151	endmodule : srx