page-program-suspend

module TopModule (
    input  logic        clk,
    input  logic        rst,
    input  logic        start_i,
    input  logic [3:0]  count_i,
    input  logic [7:0]  waddr_i,
    input  logic [31:0] wseed_i,
    input  logic        susp_req_i,
    input  logic        resume_i,
    output logic        busy_o,
    output logic        done_o,
    output logic        susp_active_o,
    output logic        susp_ack_o,
    output logic [4:0]  committed_o,
    output logic [7:0]  cur_addr_o,
    output logic [31:0] cur_data_o
);

    // States
    localparam logic [1:0] IDLE   = 2'd0;
    localparam logic [1:0] ACTIVE = 2'd1;
    localparam logic [1:0] SUSP   = 2'd2;
    localparam logic [1:0] REARM  = 2'd3;

    logic [1:0]  state;
    logic [1:0]  phase;      // cycles held within current window (0..2)
    logic [4:0]  word_idx;   // current word index k
    logic [3:0]  count_r;
    logic [7:0]  waddr_r;
    logic [31:0] wseed_r;
    logic        pending;    // pending suspend request

    // Address/data for word index k: addr = waddr+k, data = wseed ^ (k+1)
    function automatic logic [7:0] f_addr(input logic [4:0] k);
        f_addr = waddr_r + {3'd0, k};
    endfunction
    function automatic logic [31:0] f_data(input logic [4:0] k);
        f_data = wseed_r ^ ({27'd0, k} + 32'd1);
    endfunction

    always_ff @(posedge clk) begin
        if (rst) begin
            state         <= IDLE;
            phase         <= 2'd0;
            word_idx      <= 5'd0;
            count_r       <= 4'd0;
            waddr_r       <= 8'd0;
            wseed_r       <= 32'd0;
            pending       <= 1'b0;
            committed_o   <= 5'd0;
            busy_o        <= 1'b0;
            done_o        <= 1'b0;
            susp_active_o <= 1'b0;
            susp_ack_o    <= 1'b0;
            cur_addr_o    <= 8'd0;
            cur_data_o    <= 32'd0;
        end else begin
            // one-cycle pulses default low
            done_o     <= 1'b0;
            susp_ack_o <= 1'b0;

            case (state)
                // ---------------------------------------------------------
                IDLE: begin
                    if (start_i) begin
                        count_r       <= count_i;
                        waddr_r       <= waddr_i;
                        wseed_r       <= wseed_i;
                        word_idx      <= 5'd0;
                        phase         <= 2'd0;
                        committed_o   <= 5'd0;
                        busy_o        <= 1'b1;
                        susp_active_o <= 1'b0;
                        pending       <= 1'b0;
                        cur_addr_o    <= waddr_i;          // word 0 address
                        cur_data_o    <= wseed_i ^ 32'd1;  // word 0 data (k+1=1)
                        state         <= ACTIVE;
                    end
                end
                // ---------------------------------------------------------
                ACTIVE: begin
                    if (phase != 2'd2) begin
                        // holding cycle, not yet closing
                        phase <= phase + 2'd1;
                        if (susp_req_i)
                            pending <= 1'b1;
                    end else begin
                        // closing edge
                        committed_o <= committed_o + 5'd1;
                        if (word_idx == {1'b0, count_r}) begin
                            // final close
                            done_o     <= 1'b1;
                            busy_o     <= 1'b0;
                            cur_addr_o <= 8'd0;
                            cur_data_o <= 32'd0;
                            pending    <= 1'b0;   // discarded at final close
                            phase      <= 2'd0;
                            state      <= IDLE;
                        end else if (pending | susp_req_i) begin
                            // suspend on this non-final close
                            susp_active_o <= 1'b1;
                            susp_ack_o    <= 1'b1;
                            busy_o        <= 1'b1;
                            cur_addr_o    <= 8'd0;
                            cur_data_o    <= 32'd0;
                            word_idx      <= word_idx + 5'd1;  // park next word
                            pending       <= 1'b0;
                            phase         <= 2'd0;
                            state         <= SUSP;
                        end else begin
                            // open next word on this same edge
                            word_idx   <= word_idx + 5'd1;
                            phase      <= 2'd0;
                            cur_addr_o <= f_addr(word_idx + 5'd1);
                            cur_data_o <= f_data(word_idx + 5'd1);
                            state      <= ACTIVE;
                        end
                    end
                end
                // ---------------------------------------------------------
                SUSP: begin
                    // ignore start_i and susp_req_i while suspended
                    if (resume_i) begin
                        susp_active_o <= 1'b0;
                        pending       <= 1'b0;
                        busy_o        <= 1'b1;
                        cur_addr_o    <= 8'd0;
                        cur_data_o    <= 32'd0;
                        state         <= REARM;
                    end
                end
                // ---------------------------------------------------------
                REARM: begin
                    // open the parked word with a full three-cycle window
                    cur_addr_o <= f_addr(word_idx);
                    cur_data_o <= f_data(word_idx);
                    phase      <= 2'd0;
                    busy_o     <= 1'b1;
                    state      <= ACTIVE;
                end
                // ---------------------------------------------------------
                default: state <= IDLE;
            endcase
        end
    end

endmodule