bus-slave-abort-ack

module TopModule (
    input        clk,
    input        rst,
    input        cyc_i,
    input        stb_i,
    input        we_i,
    input  [1:0] adr_i,
    input  [15:0] dat_i,
    output reg   stall_o,
    output reg   ack_o,
    output reg [15:0] dat_o
);

    // Slot storage and primed bits
    reg [15:0] slot0, slot1, slot2, slot3;
    reg [3:0]  primed;

    // Read pipeline (2 stages): accept at E -> output at E+2
    reg        rd1_v, rd2_v;
    reg [15:0] rd1_data, rd2_data;

    // Write pipeline (3 stages): accept at E -> commit at E+3
    reg        w1_v, w2_v, w3_v;
    reg [1:0]  w1_adr, w2_adr, w3_adr;
    reg [15:0] w1_dat, w2_dat, w3_dat;

    // Combinational temporaries
    reg        acc, isrd, iswr;
    reg        cur_read_v, cur_wr_v;
    reg [15:0] cur_read_data, cur_wr_data;
    reg [1:0]  cadr;
    reg [15:0] oldv, newv;

    integer k;

    // mix(a,x): into lane k pack the bit-reversed source lane (k+a) mod 4.
    // Lane j = ordered bits [j, j+4, j+8, j+12]; reversed = [j+12, j+8, j+4, j].
    function [15:0] mix;
        input [1:0] a;
        input [15:0] x;
        integer i;
        reg [1:0] s;
        begin
            mix = 16'b0;
            for (i = 0; i < 4; i = i + 1) begin
                s = (i + a) & 2'b11;
                mix[i]      = x[s + 12];
                mix[i + 4]  = x[s + 8];
                mix[i + 8]  = x[s + 4];
                mix[i + 12] = x[s];
            end
        end
    endfunction

    // Select current slot value by address
    function [15:0] rdslot;
        input [1:0] a;
        begin
            case (a)
                2'd0: rdslot = slot0;
                2'd1: rdslot = slot1;
                2'd2: rdslot = slot2;
                default: rdslot = slot3;
            endcase
        end
    endfunction

    always @(posedge clk) begin
        if (rst) begin
            slot0 <= 16'b0;
            slot1 <= 16'b0;
            slot2 <= 16'b0;
            slot3 <= 16'b0;
            primed <= 4'b0;

            rd1_v <= 1'b0; rd2_v <= 1'b0;
            rd1_data <= 16'b0; rd2_data <= 16'b0;

            w1_v <= 1'b0; w2_v <= 1'b0; w3_v <= 1'b0;
            w1_adr <= 2'b0; w2_adr <= 2'b0; w3_adr <= 2'b0;
            w1_dat <= 16'b0; w2_dat <= 16'b0; w3_dat <= 16'b0;

            stall_o <= 1'b0;
            ack_o <= 1'b0;
            dat_o <= 16'b0;
        end else begin
            // Accept decision (pre-edge stall_o)
            acc  = cyc_i & stb_i & ~stall_o;
            isrd = acc & ~we_i;
            iswr = acc &  we_i;

            // Read response reaching output this edge
            cur_read_v    = rd2_v;
            cur_read_data = rd2_data;

            // Advance read pipeline
            rd2_v    <= rd1_v;
            rd2_data <= rd1_data;
            rd1_v    <= isrd;
            if (isrd)
                rd1_data <= primed[adr_i] ? mix(adr_i, rdslot(adr_i)) : 16'b0;
            else
                rd1_data <= 16'b0;

            // Write commit this edge (from stage 3), unconditional on cyc_i
            cur_wr_v    = w3_v;
            cur_wr_data = 16'b0;
            if (w3_v) begin
                cadr = w3_adr;
                oldv = rdslot(cadr);
                newv = mix(cadr, oldv) ^ w3_dat;
                case (cadr)
                    2'd0: slot0 <= newv;
                    2'd1: slot1 <= newv;
                    2'd2: slot2 <= newv;
                    default: slot3 <= newv;
                endcase
                primed[cadr] <= 1'b1;
                cur_wr_data = newv;
            end

            // Advance write pipeline
            w3_v <= w2_v; w3_adr <= w2_adr; w3_dat <= w2_dat;
            w2_v <= w1_v; w2_adr <= w1_adr; w2_dat <= w1_dat;
            w1_v <= iswr; w1_adr <= adr_i;  w1_dat <= dat_i;

            // Stall high after E+1 and E+2 of an accepted write:
            // next-state (w2|w3) == pre-edge (w1|w2)
            stall_o <= w1_v | w2_v;

            // Output edge: ack when cyc_i high; read data wins on shared edge
            if (cyc_i & (cur_read_v | cur_wr_v)) begin
                ack_o <= 1'b1;
                dat_o <= cur_read_v ? cur_read_data : cur_wr_data;
            end else begin
                ack_o <= 1'b0;
                dat_o <= 16'b0;
            end
        end
    end

endmodule