coprocessor-dispatcher-classmix

module TopModule (
  input  logic        clk,
  input  logic        rst,
  input  logic        op_valid_i,
  input  logic [1:0]  op_class_i,
  input  logic [1:0]  op_rd_i,
  input  logic [15:0] op_data_i,
  input  logic        c2_done_i,
  output logic        op_accept_o,
  output logic        wb_valid_o,
  output logic [1:0]  wb_rd_o,
  output logic [15:0] wb_data_o,
  output logic        c2_busy_o,
  output logic [3:0]  inflight_o
);

  // Class 1 slot (2-cycle latency)
  logic        c1_valid;
  logic [1:0]  c1_rd;
  logic [15:0] c1_data;

  // Class 2 slot (completes on c2_done)
  logic        c2_valid;
  logic [1:0]  c2_rd;
  logic [15:0] c2_data;
  logic        c2_ready;   // sticky readiness

  logic accept0, accept1, accept2, accept_any;
  logic req0, req1, req2;

  // Combinational accept / busy / writeback-request logic
  always_comb begin
    // Accept exactly when valid, destination not inflight, and class slot empty.
    // Class 0 has no persistent occupancy (writes back one cycle after accept).
    accept0 = op_valid_i && (op_class_i == 2'd0) && !inflight_o[op_rd_i];
    accept1 = op_valid_i && (op_class_i == 2'd1) && !inflight_o[op_rd_i] && !c1_valid;
    accept2 = op_valid_i && (op_class_i == 2'd2) && !inflight_o[op_rd_i] && !c2_valid;
    accept_any = accept0 || accept1 || accept2;   // op_class_i==3 never accepted

    op_accept_o = !rst && accept_any;
    c2_busy_o   = !rst && c2_valid;

    // Writeback requests
    req0 = accept0;    // class 0: one cycle after accept
    req1 = c1_valid;   // class 1: ready one cycle after load -> writeback next edge
    req2 = c2_ready;   // class 2: sticky ready after c2_done seen while busy
  end

  always_ff @(posedge clk) begin
    logic [3:0] inf;
    if (rst) begin
      inflight_o <= 4'd0;
      wb_valid_o <= 1'b0;
      wb_rd_o    <= 2'd0;
      wb_data_o  <= 16'd0;
      c1_valid   <= 1'b0;
      c1_rd      <= 2'd0;
      c1_data    <= 16'd0;
      c2_valid   <= 1'b0;
      c2_rd      <= 2'd0;
      c2_data    <= 16'd0;
      c2_ready   <= 1'b0;
    end else begin
      inf = inflight_o;

      // Accept: set destination bit and load the corresponding slot
      if (accept_any) inf[op_rd_i] = 1'b1;
      if (accept1) begin
        c1_valid <= 1'b1;
        c1_rd    <= op_rd_i;
        c1_data  <= op_data_i << 1;          // op_data_i * 2
      end
      if (accept2) begin
        c2_valid <= 1'b1;
        c2_rd    <= op_rd_i;
        c2_data  <= op_data_i ^ 16'hffff;
        c2_ready <= 1'b0;
      end

      // Class 2 readiness: becomes ready once c2_done is high at an edge while
      // busy; sticky until writeback.
      if (c2_valid && c2_done_i) c2_ready <= 1'b1;

      // Writeback arbitration: at most one per cycle, priority 0 > 1 > 2.
      // Non-selected ready slots stay ready (not dropped).
      wb_valid_o <= 1'b0;
      if (req0) begin
        wb_valid_o <= 1'b1;
        wb_rd_o    <= op_rd_i;
        wb_data_o  <= op_data_i + 16'd1;
        inf[op_rd_i] = 1'b0;
      end else if (req1) begin
        wb_valid_o <= 1'b1;
        wb_rd_o    <= c1_rd;
        wb_data_o  <= c1_data;
        c1_valid   <= 1'b0;
        inf[c1_rd] = 1'b0;
      end else if (req2) begin
        wb_valid_o <= 1'b1;
        wb_rd_o    <= c2_rd;
        wb_data_o  <= c2_data;
        c2_valid   <= 1'b0;
        c2_ready   <= 1'b0;
        inf[c2_rd] = 1'b0;
      end

      inflight_o <= inf;
    end
  end

endmodule