debug-halt-step-fsm

module TopModule (
    input  logic       clk,
    input  logic       rst,
    input  logic       halt_req_i,
    input  logic       resume_req_i,
    input  logic       step_req_i,
    input  logic       dbus_ren_i,
    input  logic [1:0] dbus_addr_i,
    output logic [7:0] dbus_rdata_o,
    output logic       halted_o,
    output logic       fetch_o
);

    // ------------------------------------------------------------------
    // Control FSM
    // ------------------------------------------------------------------
    typedef enum logic [2:0] {
        RUNNING = 3'd0, // fetch=1, halted=0
        HALT1   = 3'd1, // halting pipeline (fetch still high)
        HALT2   = 3'd2, // halting pipeline (fetch still high)
        HALTED  = 3'd3, // fetch=0, halted=1
        STEP1   = 3'd4, // step delay   (still halted)
        STEPF   = 3'd5, // single fetch pulse for a step
        RESUME1 = 3'd6   // resume delay (still halted)
    } state_t;

    state_t state, next_state;

    // Next-state logic
    always_comb begin
        next_state = state;
        case (state)
            RUNNING: next_state = halt_req_i ? HALT1 : RUNNING;
            HALT1:   next_state = HALT2;
            HALT2:   next_state = HALTED;
            HALTED: begin
                if (halt_req_i)        next_state = HALTED;   // halt dominates (keeps halted)
                else if (resume_req_i) next_state = RESUME1;
                else if (step_req_i)   next_state = STEP1;
                else                   next_state = HALTED;
            end
            STEP1:   next_state = STEPF;
            STEPF:   next_state = HALTED;
            RESUME1: next_state = RUNNING;
            default: next_state = RUNNING;
        endcase
    end

    // Moore outputs (registered from next_state)
    function automatic logic fetch_of(state_t s);
        case (s)
            RUNNING, HALT1, HALT2, STEPF: fetch_of = 1'b1;
            default:                      fetch_of = 1'b0;
        endcase
    endfunction

    function automatic logic halted_of(state_t s);
        case (s)
            HALTED, STEP1, RESUME1: halted_of = 1'b1;
            default:                halted_of = 1'b0;
        endcase
    endfunction

    // ------------------------------------------------------------------
    // Debug bus ROM (independent of core state)
    // ------------------------------------------------------------------
    function automatic logic [7:0] mem_read(logic [1:0] a);
        case (a)
            2'd0:    mem_read = 8'h5A;
            2'd1:    mem_read = 8'hC3;
            2'd2:    mem_read = 8'h0F;
            2'd3:    mem_read = 8'h96;
            default: mem_read = 8'h00;
        endcase
    endfunction

    // dbus read pipeline: address/ren sampled at edge R, data at edge R+1
    logic       ren_q;
    logic [1:0] addr_q;

    // ------------------------------------------------------------------
    // Registered state + outputs
    // ------------------------------------------------------------------
    always_ff @(posedge clk) begin
        if (rst) begin
            state        <= RUNNING;
            fetch_o      <= 1'b0;
            halted_o     <= 1'b0;
            dbus_rdata_o <= 8'h00;
            ren_q        <= 1'b0;
            addr_q       <= 2'd0;
        end else begin
            state    <= next_state;
            fetch_o  <= fetch_of(next_state);
            halted_o <= halted_of(next_state);

            // dbus: stage the request, then present the data one edge later,
            // holding the value while ren is low.
            ren_q  <= dbus_ren_i;
            addr_q <= dbus_addr_i;
            if (ren_q)
                dbus_rdata_o <= mem_read(addr_q);
        end
    end

endmodule