serial-break-resync

// UART receiver with break detection and post-break framing-error propagation.
module TopModule #(
    parameter BITLEN = 16
) (
    input  logic       clk,
    input  logic       rst,
    input  logic       rx_i,
    output logic [7:0] data_o,
    output logic       valid_o,
    output logic       frame_err_o,
    output logic       break_o
);

    localparam int HALF   = BITLEN/2;      // floored half bit period
    localparam int SIXBIT = 6*BITLEN;      // six continuous bit periods

    // synchronizer (two flops); sync1 is "the synchronized line"
    logic sync0, sync1;

    // FSM states
    localparam logic [1:0] S_IDLE    = 2'd0; // waiting for a start edge
    localparam logic [1:0] S_RECV    = 2'd1; // sampling data + stop bits
    localparam logic [1:0] S_BREAK   = 2'd2; // break asserted, line held low
    localparam logic [1:0] S_RECOVER = 2'd3; // after break, waiting 6 high periods
    logic [1:0] state;

    // continuous low / high run lengths on the synchronized line
    logic [31:0] low_run, high_run;

    // per-bit sample counter and bit index within a frame
    logic [31:0] samp_cnt;
    logic [3:0]  bit_idx;    // 0..7 = data bits, 8 = stop bit
    logic [7:0]  data_reg;

    // pending forced-framing-error count (d from the interrupting break)
    logic [3:0]  pend_cnt;

    always_ff @(posedge clk) begin : main
        logic [31:0] cur_low;
        logic [31:0] cur_high;

        if (rst) begin
            sync0       <= 1'b1;
            sync1       <= 1'b1;
            state       <= S_IDLE;
            low_run     <= 32'd0;
            high_run    <= 32'd0;
            samp_cnt    <= 32'd0;
            bit_idx     <= 4'd0;
            data_reg    <= 8'd0;
            pend_cnt    <= 4'd0;
            data_o      <= 8'd0;
            valid_o     <= 1'b0;
            frame_err_o <= 1'b0;
            break_o     <= 1'b0;
        end else begin
            // one-cycle pulse outputs default low; break_o is a level (holds)
            valid_o     <= 1'b0;
            frame_err_o <= 1'b0;

            // two-flop synchronizer
            sync0 <= rx_i;
            sync1 <= sync0;

            // consecutive low/high run lengths (including the current cycle)
            if (sync1 == 1'b0) begin
                cur_low  = low_run + 32'd1;
                cur_high = 32'd0;
            end else begin
                cur_low  = 32'd0;
                cur_high = high_run + 32'd1;
            end
            low_run  <= cur_low;
            high_run <= cur_high;

            // ---- break detection: preempts an idle wait or an in-flight frame ----
            if ((state == S_IDLE || state == S_RECV) && (cur_low == SIXBIT)) begin
                break_o  <= 1'b1;
                state    <= S_BREAK;
                // d = data bits the interrupted byte sampled (0 if no frame)
                pend_cnt <= (state == S_RECV) ? bit_idx : 4'd0;
            end else begin
                case (state)
                    // idle: accept a start once a fresh low reaches half a bit period
                    S_IDLE: begin
                        if (cur_low == HALF) begin
                            state    <= S_RECV;
                            samp_cnt <= 32'd0;
                            bit_idx  <= 4'd0;
                        end
                    end

                    // receiving: sample each bit at its centre, BITLEN cycles apart
                    S_RECV: begin
                        if (samp_cnt == BITLEN-1) begin
                            samp_cnt <= 32'd0;
                            if (bit_idx < 4'd8) begin
                                data_reg[bit_idx] <= sync1;    // data bit, LSB first
                                bit_idx           <= bit_idx + 4'd1;
                            end else begin
                                // stop bit: deliver the byte
                                valid_o     <= 1'b1;
                                data_o      <= data_reg;
                                frame_err_o <= (sync1 == 1'b0) || (pend_cnt != 4'd0);
                                if (pend_cnt != 4'd0)
                                    pend_cnt <= pend_cnt - 4'd1;
                                state <= S_IDLE;
                            end
                        end else begin
                            samp_cnt <= samp_cnt + 32'd1;
                        end
                    end

                    // break held: wait for the line to return high
                    S_BREAK: begin
                        if (sync1 == 1'b1) begin
                            break_o <= 1'b0;
                            state   <= S_RECOVER;
                        end
                    end

                    // recovery: require six continuous high bit periods; any low restarts
                    S_RECOVER: begin
                        if (cur_high >= SIXBIT)
                            state <= S_IDLE;
                    end

                    default: state <= S_IDLE;
                endcase
            end
        end
    end
endmodule