apb-lite-slave-regfile

// APB slave with 4 word registers + off-map handling.
// - Setup phase:  psel=1, penable=0
// - Access phase: psel=1, penable=1  (only these complete transfers)
module TopModule (
    input               clk,
    input               rst,       // synchronous, active high
    input               psel,
    input               penable,
    input               pwrite,
    input      [3:0]    paddr,
    input      [31:0]   pwdata,
    output reg [31:0]   prdata,
    output reg          pready,
    output reg          pslverr
);

    // Writable / stored state
    reg [31:0] reg0;
    reg [7:0]  reg1_low;
    reg [31:0] reg3;
    reg        word3_ready;   // 1 => word-3 transaction has passed its first (wait) access cycle

    wire access  = psel & penable;
    wire off_map = (paddr >= 4'd4);

    // ---- Combinational pready / pslverr ----
    always @(*) begin
        pready  = 1'b0;
        pslverr = 1'b0;
        if (!rst && access) begin
            if (off_map) begin
                pready  = 1'b1;
                pslverr = 1'b1;
            end else if (paddr == 4'd3) begin
                pready  = word3_ready;   // first access cycle waits (0), later cycles ready
                pslverr = 1'b0;
            end else begin
                pready  = 1'b1;
                pslverr = 1'b0;
            end
        end
    end

    // ---- Combinational prdata ----
    always @(*) begin
        prdata = 32'd0;
        if (!rst && access && !pwrite && !off_map) begin
            case (paddr[1:0])
                2'd0: prdata = reg0;
                2'd1: prdata = {24'd0, reg1_low};
                2'd2: prdata = 32'h0AB15001;      // read-only constant
                2'd3: prdata = reg3;
            endcase
        end
    end

    // ---- Sequential state ----
    always @(posedge clk) begin
        if (rst) begin
            reg0        <= 32'd0;
            reg1_low    <= 8'd0;
            reg3        <= 32'd0;
            word3_ready <= 1'b0;
        end else begin
            // Track word-3 wait state: set during a word-3 access cycle so the
            // next held access cycle reports ready; cleared otherwise (incl. setup).
            if (access && (paddr == 4'd3))
                word3_ready <= 1'b1;
            else
                word3_ready <= 1'b0;

            // Writes commit only on a completing access cycle (pready=1, no error).
            if (access && pwrite && pready && !pslverr) begin
                case (paddr[1:0])
                    2'd0: reg0     <= pwdata;
                    2'd1: reg1_low <= pwdata[7:0];
                    2'd2: ;                         // word 2 read-only: write ignored
                    2'd3: reg3     <= pwdata;
                endcase
            end
        end
    end

endmodule