serial-break-resync

module TopModule #(
  parameter int BITLEN = 16
) (
  input  logic       clk,
  input  logic       rst,
  input  logic       rx_i,
  output logic [7:0] data_o,
  output logic       valid_o,
  output logic       frame_err_o,
  output logic       break_o
);

  // Half a bit period (floored), a full break span (six bit periods),
  // and a counter width big enough to reach it.
  localparam int HALF = BITLEN/2;
  localparam int BRK  = 6*BITLEN;
  localparam int CW   = $clog2(6*BITLEN+1);

  // ---- two-flop synchronizer (the line idles high) --------------------
  logic rx_meta, rx_sync;
  always_ff @(posedge clk) begin
    if (rst) begin
      rx_meta <= 1'b1;
      rx_sync <= 1'b1;
    end else begin
      rx_meta <= rx_i;
      rx_sync <= rx_meta;
    end
  end

  // ---- continuous low / high run counters -----------------------------
  logic [CW-1:0] low_cnt, high_cnt;

  // ---- combinational break / recovery events --------------------------
  logic set_break, brk_rise, high_reached;
  assign set_break    = (~rx_sync) & (low_cnt  >= CW'(BRK-1));
  assign brk_rise     = set_break & ~break_o;               // rising edge of break
  assign high_reached = ( rx_sync) & (high_cnt >= CW'(BRK-1));

  // ---- frame reception FSM --------------------------------------------
  typedef enum logic [1:0] {IDLE, DATA, STOP} state_t;
  state_t        state;
  logic [CW-1:0] timer;        // cycles until next bit-center sample
  logic [3:0]    bit_idx;      // data bits sampled so far (0..8)
  logic [7:0]    data_sh;      // shift register (LSB first)
  logic          locked;       // post-break: block starts until 6-bit high
  logic [3:0]    ferr_pending; // remaining bytes to force frame_err (= d)

  always_ff @(posedge clk) begin
    if (rst) begin
      low_cnt      <= '0;
      high_cnt     <= '0;
      state        <= IDLE;
      timer        <= '0;
      bit_idx      <= '0;
      data_sh      <= '0;
      locked       <= 1'b0;
      ferr_pending <= '0;
      data_o       <= '0;
      valid_o      <= 1'b0;
      frame_err_o  <= 1'b0;
      break_o      <= 1'b0;
    end else begin
      // registered pulse outputs default low
      valid_o     <= 1'b0;
      frame_err_o <= 1'b0;

      // continuous-run counters (saturate at BRK)
      if (rx_sync) begin
        high_cnt <= (high_cnt == CW'(BRK)) ? CW'(BRK) : high_cnt + 1'b1;
        low_cnt  <= '0;
      end else begin
        low_cnt  <= (low_cnt  == CW'(BRK)) ? CW'(BRK) : low_cnt + 1'b1;
        high_cnt <= '0;
      end

      // break is a registered level: high while six low periods have elapsed
      break_o <= set_break;

      // lock after a break; release once the line holds high six bit periods
      if (brk_rise)          locked <= 1'b1;
      else if (high_reached) locked <= 1'b0;

      // A break preempts any frame in progress.
      if (brk_rise) begin
        // d = data bits the interrupted byte sampled (0 if none / no frame);
        // a further break replaces any pending count with its own d.
        ferr_pending <= (state == DATA || state == STOP) ? bit_idx : 4'd0;
        state        <= IDLE;
        bit_idx      <= '0;
        timer        <= '0;
      end else begin
        case (state)
          IDLE: begin
            // Accept a start the cycle a fresh low reaches half a bit period.
            if (!locked && !rx_sync && (low_cnt == CW'(HALF))) begin
              state   <= DATA;
              timer   <= CW'(BITLEN-1);
              bit_idx <= '0;
              data_sh <= '0;
            end
          end
          DATA: begin
            if (timer == '0) begin
              data_sh <= {rx_sync, data_sh[7:1]};   // LSB first
              timer   <= CW'(BITLEN-1);
              bit_idx <= bit_idx + 1'b1;
              if (bit_idx == 4'd7)
                state <= STOP;
            end else begin
              timer <= timer - 1'b1;
            end
          end
          STOP: begin
            if (timer == '0) begin
              valid_o     <= 1'b1;
              data_o      <= data_sh;
              // frame error if stop bit low, or forced for the next d bytes
              frame_err_o <= (~rx_sync) | (ferr_pending != 0);
              if (ferr_pending != 0)
                ferr_pending <= ferr_pending - 1'b1;
              state   <= IDLE;
              bit_idx <= '0;
            end else begin
              timer <= timer - 1'b1;
            end
          end
          default: state <= IDLE;
        endcase
      end
    end
  end

endmodule