coprocessor-dispatcher-classmix

module TopModule (
    input               clk,
    input               rst,
    input               op_valid_i,
    input        [1:0]  op_class_i,
    input        [1:0]  op_rd_i,
    input        [15:0] op_data_i,
    input               c2_done_i,
    output logic        op_accept_o,
    output logic        wb_valid_o,
    output logic [1:0]  wb_rd_o,
    output logic [15:0] wb_data_o,
    output logic        c2_busy_o,
    output logic [3:0]  inflight_o
);

    // ---- Slot state (registered) ----
    // Class 0 : latency 1  -> ready as soon as stored
    logic        c0_valid;
    logic [1:0]  c0_rd;
    logic [15:0] c0_data;

    // Class 1 : latency 2  -> one wait cycle after store
    logic        c1_valid;
    logic        c1_wait;
    logic [1:0]  c1_rd;
    logic [15:0] c1_data;

    // Class 2 : variable   -> ready sticky once c2_done seen while busy
    logic        c2_valid;
    logic        c2_ready;
    logic [1:0]  c2_rd;
    logic [15:0] c2_data;

    // ---- Combinational readiness / writeback selection ----
    logic ready0, ready1, ready2;
    logic fire0, fire1, fire2;
    logic empty;

    always_comb begin
        // Acceptance
        unique case (op_class_i)
            2'd0:    empty = ~c0_valid;
            2'd1:    empty = ~c1_valid;
            2'd2:    empty = ~c2_valid;
            default: empty = 1'b0;   // class 3 never accepted
        endcase
        op_accept_o = op_valid_i & (op_class_i != 2'd3)
                    & ~inflight_o[op_rd_i] & empty;

        // Ready slots
        ready0 = c0_valid;
        ready1 = c1_valid & ~c1_wait;
        ready2 = c2_valid & c2_ready;

        // Single writeback per cycle, priority 0 > 1 > 2
        fire0 = ready0;
        fire1 = ready1 & ~ready0;
        fire2 = ready2 & ~ready0 & ~ready1;

        wb_valid_o = ready0 | ready1 | ready2;
        if (fire0) begin
            wb_rd_o   = c0_rd;
            wb_data_o = c0_data;
        end else if (fire1) begin
            wb_rd_o   = c1_rd;
            wb_data_o = c1_data;
        end else if (fire2) begin
            wb_rd_o   = c2_rd;
            wb_data_o = c2_data;
        end else begin
            wb_rd_o   = 2'd0;
            wb_data_o = 16'd0;
        end

        // Class 2 busy whenever its slot is occupied
        c2_busy_o = c2_valid;
    end

    // Accept qualifiers per class
    logic acc0, acc1, acc2;
    assign acc0 = op_accept_o & (op_class_i == 2'd0);
    assign acc1 = op_accept_o & (op_class_i == 2'd1);
    assign acc2 = op_accept_o & (op_class_i == 2'd2);

    // ---- Sequential update ----
    always_ff @(posedge clk) begin
        if (rst) begin
            c0_valid   <= 1'b0;
            c0_rd      <= 2'd0;
            c0_data    <= 16'd0;
            c1_valid   <= 1'b0;
            c1_wait    <= 1'b0;
            c1_rd      <= 2'd0;
            c1_data    <= 16'd0;
            c2_valid   <= 1'b0;
            c2_ready   <= 1'b0;
            c2_rd      <= 2'd0;
            c2_data    <= 16'd0;
            inflight_o <= 4'd0;
        end else begin
            // Class 1 wait countdown
            if (c1_valid & c1_wait)
                c1_wait <= 1'b0;

            // Class 2 readiness becomes sticky once done seen while busy
            if (c2_valid & c2_done_i)
                c2_ready <= 1'b1;

            // Writebacks free slots and clear inflight bits
            if (fire0) begin
                c0_valid          <= 1'b0;
                inflight_o[c0_rd] <= 1'b0;
            end
            if (fire1) begin
                c1_valid          <= 1'b0;
                inflight_o[c1_rd] <= 1'b0;
            end
            if (fire2) begin
                c2_valid          <= 1'b0;
                c2_ready          <= 1'b0;
                inflight_o[c2_rd] <= 1'b0;
            end

            // Accept & store (at most one per cycle)
            if (acc0) begin
                c0_valid          <= 1'b1;
                c0_rd             <= op_rd_i;
                c0_data           <= op_data_i + 16'd1;
                inflight_o[op_rd_i] <= 1'b1;
            end
            if (acc1) begin
                c1_valid          <= 1'b1;
                c1_wait           <= 1'b1;
                c1_rd             <= op_rd_i;
                c1_data           <= op_data_i << 1;
                inflight_o[op_rd_i] <= 1'b1;
            end
            if (acc2) begin
                c2_valid          <= 1'b1;
                c2_ready          <= 1'b0;
                c2_rd             <= op_rd_i;
                c2_data           <= op_data_i ^ 16'hffff;
                inflight_o[op_rd_i] <= 1'b1;
            end
        end
    end

endmodule