byte-serial-round-scheduler

module TopModule (
    input               clk,
    input               rst_n,
    input               start,
    input      [127:0]  block_in,
    input      [127:0]  round_key0,
    input      [3:0]    num_rounds,
    input               reseed,
    input      [3:0]    reseed_round,
    output reg          ready,
    output reg          result_valid,
    output reg [127:0]  block_out
);

    // internal state
    reg          busy;
    reg [127:0]  state;
    reg [127:0]  rk;
    reg [3:0]    nrounds;
    reg [3:0]    round_index;   // number of completed rounds (0..nrounds-1 while running)
    reg [4:0]    slot_idx;      // 0..15 byte slots, 16 = key-mix slot
    reg [7:0]    start_fb;      // this round's start feedback
    reg [7:0]    prev_byte;     // previous byte slot's output

    always @(posedge clk) begin : proc
        reg [7:0] blsb;   // byte LSB bit index
        reg [7:0] cb;     // current byte
        reg [7:0] fb;     // feedback
        reg [7:0] xo;     // xored
        reg [7:0] ro;     // rotated
        reg [7:0] ob;     // output byte

        if (!rst_n) begin
            ready        <= 1'b1;
            result_valid <= 1'b0;
            block_out    <= 128'b0;
            busy         <= 1'b0;
            state        <= 128'b0;
            rk           <= 128'b0;
            nrounds      <= 4'b0;
            round_index  <= 4'b0;
            slot_idx     <= 5'b0;
            start_fb     <= 8'b0;
            prev_byte    <= 8'b0;
        end else begin
            result_valid <= 1'b0;   // default: deassert (overridden on finish)

            if (!busy) begin
                // idle: ready held high; accept start
                if (start && ready) begin
                    state       <= block_in;
                    rk          <= round_key0;
                    nrounds     <= num_rounds;
                    round_index <= 4'd0;
                    start_fb    <= 8'd0;        // {4'b0, round_index=0}
                    prev_byte   <= 8'd0;
                    slot_idx    <= 5'd0;
                    busy        <= 1'b1;
                    ready       <= 1'b0;
                end
            end else begin
                if (slot_idx <= 5'd15) begin
                    // ---- byte slot ----
                    blsb = {slot_idx[3:2], 5'b00000} + 8'd24 - {slot_idx[1:0], 3'b000};
                    cb   = state[blsb +: 8];
                    fb   = (slot_idx == 5'd0) ? start_fb : prev_byte;
                    xo   = cb ^ fb;
                    ro   = {xo[6:0], xo[7]};        // rol1
                    ob   = ro ^ 8'h63;

                    state[blsb +: 8] <= ob;
                    prev_byte        <= ob;
                    slot_idx         <= slot_idx + 5'd1;
                end else begin
                    // ---- key-mix slot ----
                    if (round_index + 4'd1 == nrounds) begin
                        // finishing slot
                        block_out    <= state ^ rk;
                        result_valid <= 1'b1;
                        ready        <= 1'b1;
                        busy         <= 1'b0;
                        slot_idx     <= 5'd0;
                    end else begin
                        state       <= state ^ rk;
                        round_index <= round_index + 4'd1;
                        start_fb    <= reseed ? {4'b0, reseed_round}
                                              : {4'b0, round_index};
                        prev_byte   <= 8'd0;
                        slot_idx    <= 5'd0;
                    end
                end
            end
        end
    end

endmodule

module tb;
  reg clk=0, rst_n, start, reseed;
  reg [127:0] block_in, round_key0;
  reg [3:0] num_rounds, reseed_round;
  wire ready, result_valid;
  wire [127:0] block_out;

  TopModule dut(.clk(clk),.rst_n(rst_n),.start(start),.block_in(block_in),
    .round_key0(round_key0),.num_rounds(num_rounds),.reseed(reseed),
    .reseed_round(reseed_round),.ready(ready),.result_valid(result_valid),
    .block_out(block_out));

  always #5 clk=~clk;

  // reference model: compute final block for given inputs & a reseed decision
  // reseed_en applies at every non-final key-mix (constant here for test)
  function [127:0] ref_model(input [127:0] bin, input [127:0] key,
                             input [3:0] nr, input use_reseed, input [3:0] rr);
    reg [127:0] st; integer r, i, c, j, lsb; reg [7:0] sfb, fb, prev, b, o;
    begin
      st = bin;
      for (r=0; r<nr; r=r+1) begin
        if (r==0) sfb = 8'd0;
        else sfb = use_reseed ? {4'b0, rr} : {4'b0, (r-1)}; // pre-increment round_index
        prev = 8'd0;
        for (i=0; i<16; i=i+1) begin
          c = i/4; j = i%4; lsb = 32*c + 24 - 8*j;
          b = st[lsb +: 8];
          fb = (i==0) ? sfb : prev;
          o = ({b^fb} << 1) | (({b^fb} >> 7) & 8'h01); // rol1
          o = o ^ 8'h63;
          st[lsb +: 8] = o;
          prev = o;
        end
        st = st ^ key; // key-mix
      end
      ref_model = st;
    end
  endfunction

  integer errors=0;
  task run_op(input [127:0] bin, input [127:0] key, input [3:0] nr,
              input rs, input [3:0] rr);
    reg [127:0] exp;
    begin
      @(negedge clk);
      // wait ready
      while(!ready) @(negedge clk);
      start=1; block_in=bin; round_key0=key; num_rounds=nr; reseed=rs; reseed_round=rr;
      @(negedge clk); start=0;
      // wait for result
      while(!result_valid) @(negedge clk);
      exp = ref_model(bin,key,nr,rs,rr);
      if (block_out !== exp) begin
        errors=errors+1;
        $display("FAIL nr=%0d rs=%0d got=%h exp=%h",nr,rs,block_out,exp);
      end else
        $display("PASS nr=%0d rs=%0d out=%h",nr,rs,block_out);
    end
  endtask

  initial begin
    rst_n=0; start=0; reseed=0; block_in=0; round_key0=0; num_rounds=1; reseed_round=0;
    @(negedge clk); @(negedge clk); rst_n=1;
    if(!ready) begin $display("FAIL ready not high after reset"); errors=errors+1; end
    run_op(128'h0123456789abcdef_fedcba9876543210, 128'hdeadbeef_cafebabe_00112233_44556677, 1, 0, 0);
    run_op(128'h0123456789abcdef_fedcba9876543210, 128'hdeadbeef_cafebabe_00112233_44556677, 5, 0, 0);
    run_op(128'hffffffff_ffffffff_00000000_11111111, 128'h1, 10, 1, 4'd7);
    run_op(128'ha5a5a5a5_5a5a5a5a_deadbeef_12345678, 128'hcccccccc_dddddddd_eeeeeeee_ffffffff, 15, 1, 4'd3);
    run_op(128'h0, 128'h0, 3, 0, 0);
    // back-to-back
    run_op(128'h11223344_55667788_99aabbcc_ddeeff00, 128'h0f0f0f0f_0f0f0f0f_f0f0f0f0_f0f0f0f0, 2, 0, 0);
    if(errors==0) $display("ALL TESTS PASSED"); else $display("%0d ERRORS",errors);
    $finish;
  end
endmodule