serial-break-resync

// UART-style receiver with break detection.
//
// A byte  : 1 low start bit, 8 data bits (LSB first), 1 high stop bit,
//           each BITLEN clock cycles.  Line idles high.
// Start   : accepted the cycle a fresh continuous low (measured from the
//           high->low edge) reaches floor(BITLEN/2); a shorter low is ignored.
// Sampling: 8 data bits then the stop bit at bit-period centers.
// break_o : level, high once the synchronized line has been continuously low
//           for six bit periods, until the line is high again.  A break is
//           shorter than a byte and preempts any frame in progress (dropped).
//           After break falls, no start is accepted until the line holds high
//           for six bit periods (any low restarts the wait).
// Let d be the number of data bits the interrupted byte sampled (0 if none):
//           the next d delivered bytes force frame_err_o high; a further break
//           replaces any pending count with its own d.

module TopModule #(
    parameter BITLEN = 16
)(
    input  logic       clk,
    input  logic       rst,
    input  logic       rx_i,
    output logic [7:0] data_o,
    output logic       valid_o,
    output logic       frame_err_o,
    output logic       break_o
);

    localparam int HALF     = BITLEN / 2;      // floor(BITLEN/2)
    localparam int BREAKLEN = 6 * BITLEN;      // six bit periods
    localparam int CW       = $clog2(6 * BITLEN + 2);

    // two-flop synchronizer for rx_i
    logic sync1, sync2;

    logic [CW:0] low_run, high_run;   // continuous low / high run lengths
    logic        armed;               // start acceptance enabled
    logic        active;              // a frame is being received
    logic [CW:0] phase_cnt;           // cycles since last sample point
    logic [3:0]  data_idx;            // number of data bits sampled (0..8)
    logic [7:0]  shreg;               // received data (LSB first)
    logic [3:0]  pending_err;         // remaining bytes forced to frame error

    always_ff @(posedge clk) begin
        if (rst) begin
            sync1       <= 1'b1;
            sync2       <= 1'b1;
            low_run     <= '0;
            high_run    <= '0;
            armed       <= 1'b1;
            active      <= 1'b0;
            phase_cnt   <= '0;
            data_idx    <= '0;
            shreg       <= '0;
            pending_err <= '0;
            data_o      <= '0;
            valid_o     <= 1'b0;
            frame_err_o <= 1'b0;
            break_o     <= 1'b0;
        end else begin
            logic        cur;
            logic [CW:0] nlow, nhigh;
            logic        brk;
            logic        newly_break;

            // synchronizer
            sync1 <= rx_i;
            sync2 <= sync1;
            cur    = sync2;            // the synchronized line

            // continuous low / high run counters (saturating)
            if (cur == 1'b0) begin
                nlow  = (low_run >= BREAKLEN) ? BREAKLEN[CW:0] : low_run + 1'b1;
                nhigh = '0;
            end else begin
                nlow  = '0;
                nhigh = (high_run >= BREAKLEN) ? BREAKLEN[CW:0] : high_run + 1'b1;
            end
            low_run  <= nlow;
            high_run <= nhigh;

            // break level
            if (cur == 1'b1)
                brk = 1'b0;
            else if (nlow >= BREAKLEN)
                brk = 1'b1;
            else
                brk = break_o;
            break_o     <= brk;
            newly_break  = brk & ~break_o;    // rising edge of break

            // arm / recover
            if (newly_break)
                armed <= 1'b0;
            else if (!armed && nhigh >= BREAKLEN)
                armed <= 1'b1;

            // pulse outputs default low
            valid_o     <= 1'b0;
            frame_err_o <= 1'b0;

            if (newly_break) begin
                // break preempts any frame; record how many data bits it sampled
                active      <= 1'b0;
                pending_err <= active ? data_idx : 4'd0;
            end else if (active) begin
                if (phase_cnt + 1 == BITLEN) begin
                    phase_cnt <= '0;
                    if (data_idx < 8) begin
                        shreg    <= {cur, shreg[7:1]};   // LSB first
                        data_idx <= data_idx + 1'b1;
                    end else begin
                        // stop bit sampled -> deliver the byte
                        valid_o     <= 1'b1;
                        data_o      <= shreg;
                        frame_err_o <= (cur == 1'b0) || (pending_err != 0);
                        if (pending_err != 0)
                            pending_err <= pending_err - 1'b1;
                        active <= 1'b0;
                    end
                end else begin
                    phase_cnt <= phase_cnt + 1'b1;
                end
            end else begin
                // idle: accept a fresh start at half a bit period of low
                if (armed && cur == 1'b0 && nlow == HALF) begin
                    active    <= 1'b1;
                    phase_cnt <= '0;
                    data_idx  <= '0;
                end
            end
        end
    end

endmodule