Wait-state register-file completer

Chunk ID: eae0b4
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Output:
apb_core/rtl/apb_slave.sv
apb_core/rtl/apb_pkg.sv
apb_core/rtl/apb_top.sv

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Output:
sed: can't read rtl/apb_slave.sv: No such file or directory

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Output:
./apb_core/rtl/apb_top.sv
./apb_core/rtl/apb_pkg.sv
./apb_core/rtl/apb_slave.sv

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Output:
//==============================================================================
// apb_slave.sv
//
// Wait-state register-file completer for a two-phase select/enable handshake.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and the state registers are provided. The
//  handshake control, the wait-cycle counting, the register file commit and
//  the outputs are left as a TODO and currently drive constant zeros, so the
//  completer never raises pready and the verifier FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the
//  module name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module apb_slave #(
    parameter AW   = 6,
    parameter DW   = 32,
    parameter NREG = 16
) (
    input  logic                  pclk,
    input  logic                  presetn,
    input  logic                  psel,
    input  logic                  penable,
    input  logic                  pwrite,
    input  logic [AW-1:0]         paddr,
    input  logic [DW-1:0]         pwdata,
    output logic                  pready,
    output logic [DW-1:0]         prdata,
    output logic                  pslverr
);

  // ---------------------------------------------------------------------------
  // State registers (provided). Add whatever combinational helpers you need.
  // ---------------------------------------------------------------------------
  logic [DW-1:0] regfile [0:NREG-1];
  logic [1:0]    state;
  logic [1:0]    acc;        // access-edge counter
  integer        i;

  // ===========================================================================
  // TODO: IMPLEMENT THE COMPLETER.
  //   * walk the two-phase handshake (setup for one clk, then access);
  //   * insert the required number of wait cycles before completing, and pulse
  //     pready for exactly the completion clk;
  //   * commit a write / drive a read on the completion clk per instruction.md;
  //   * flag out-of-range accesses on the completion clk with no register effect;
  //   * presetn is asynchronous, active low, and clears the file and outputs.
  //
  // The placeholder below keeps the module compilable but INCORRECT.
  // ===========================================================================
  always_ff @(posedge pclk or negedge presetn) begin
    if (!presetn) begin
      for (i = 0; i < NREG; i = i + 1) regfile[i] <= {DW{1'b0}};
      state <= 2'd0;
      acc   <= 2'd0;
    end else begin
      // TODO: replace with the real handshake + datapath.
      state <= state;
      acc   <= acc;
    end
  end

  // TODO: replace these placeholder outputs with the real ones.
  assign pready  = 1'b0;
  assign prdata  = {DW{1'b0}};
  assign pslverr = 1'b0;

endmodule : apb_slave

Chunk ID: b032b8
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Output:
//==============================================================================
// apb_pkg.sv
//
// Shared geometry for the wait-state register completer. The block exposes a
// register file of NREG words, each DW bits wide, addressed by an AW-bit word
// address. Parameters are declared without an explicit data type for broad
// simulator compatibility (Icarus Verilog 11); they default to integer
// constants, which is sufficient here.
//
// DO NOT change this file.
//==============================================================================
`ifndef APB_PKG_SV
`define APB_PKG_SV

package apb_pkg;

  localparam AW   = 6;    // address width (word address)
  localparam DW   = 32;   // data word width
  localparam NREG = 16;   // number of in-range registers (addr 0..NREG-1)

endpackage : apb_pkg

`endif // APB_PKG_SV

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Output:
//==============================================================================
// apb_top.sv
//
// Thin integration wrapper. The verification environment drives this wrapper so
// that the instantiation wiring is exercised alongside the completer itself. It
// instantiates apb_slave with the project-default geometry from apb_pkg.
//
// DO NOT change this file.
//==============================================================================
`timescale 1ns/1ps
`include "apb_pkg.sv"

module apb_top (
    input  logic                          pclk,
    input  logic                          presetn,
    input  logic                          psel,
    input  logic                          penable,
    input  logic                          pwrite,
    input  logic [apb_pkg::AW-1:0]        paddr,
    input  logic [apb_pkg::DW-1:0]        pwdata,
    output logic                          pready,
    output logic [apb_pkg::DW-1:0]        prdata,
    output logic                          pslverr
);

  // Bare instantiation: the completer carries its own default geometry, so a
  // submission needs no parameter override to elaborate correctly.
  apb_slave u_apb_slave (
      .pclk    (pclk),
      .presetn (presetn),
      .psel    (psel),
      .penable (penable),
      .pwrite  (pwrite),
      .paddr   (paddr),
      .pwdata  (pwdata),
      .pready  (pready),
      .prdata  (prdata),
      .pslverr (pslverr)
  );

endmodule : apb_top

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Output:

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Output:
/bin/bash: line 1: git: command not found

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Output:
PASS

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Output:
//==============================================================================
// apb_slave.sv
//
// Wait-state register-file completer for a two-phase select/enable handshake.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and the state registers are provided. The
//  handshake control, the wait-cycle counting, the register file commit and
//  the outputs are left as a TODO and currently drive constant zeros, so the
//  completer never raises pready and the verifier FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the
//  module name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module apb_slave #(
    parameter AW   = 6,
    parameter DW   = 32,
    parameter NREG = 16
) (
    input  logic                  pclk,
    input  logic                  presetn,
    input  logic                  psel,
    input  logic                  penable,
    input  logic                  pwrite,
    input  logic [AW-1:0]         paddr,
    input  logic [DW-1:0]         pwdata,
    output logic                  pready,
    output logic [DW-1:0]         prdata,
    output logic                  pslverr
);

  // ---------------------------------------------------------------------------
  // State registers (provided). Add whatever combinational helpers you need.
  // ---------------------------------------------------------------------------
  logic [DW-1:0] regfile [0:NREG-1];
  logic [1:0]    state;
  logic [1:0]    acc;        // access-edge counter
  logic          req_write;
  logic [AW-1:0] req_addr;
  logic [DW-1:0] req_wdata;
  integer        i;

  localparam logic [1:0] ST_IDLE   = 2'd0;
  localparam logic [1:0] ST_ACCESS = 2'd1;

  logic complete_now;
  logic req_in_range;

  assign complete_now = req_write ? (acc == 2'd2) : (acc == 2'd1);
  assign req_in_range = (req_addr < NREG);

  // ===========================================================================
  // TODO: IMPLEMENT THE COMPLETER.
  //   * walk the two-phase handshake (setup for one clk, then access);
  //   * insert the required number of wait cycles before completing, and pulse
  //     pready for exactly the completion clk;
  //   * commit a write / drive a read on the completion clk per instruction.md;
  //   * flag out-of-range accesses on the completion clk with no register effect;
  //   * presetn is asynchronous, active low, and clears the file and outputs.
  //
  // The placeholder below keeps the module compilable but INCORRECT.
  // ===========================================================================
  always_ff @(posedge pclk or negedge presetn) begin
    if (!presetn) begin
      for (i = 0; i < NREG; i = i + 1) regfile[i] <= {DW{1'b0}};
      state     <= ST_IDLE;
      acc       <= 2'd0;
      req_write <= 1'b0;
      req_addr  <= {AW{1'b0}};
      req_wdata <= {DW{1'b0}};
      pready    <= 1'b0;
      prdata    <= {DW{1'b0}};
      pslverr   <= 1'b0;
    end else begin
      pready  <= 1'b0;
      prdata  <= {DW{1'b0}};
      pslverr <= 1'b0;

      case (state)
        ST_IDLE: begin
          acc <= 2'd0;

          if (psel && !penable) begin
            req_write <= pwrite;
            req_addr  <= paddr;
            req_wdata <= pwdata;
            state     <= ST_ACCESS;
          end else begin
            state <= ST_IDLE;
          end
        end

        ST_ACCESS: begin
          if (psel && penable) begin
            if (complete_now) begin
              pready  <= 1'b1;
              pslverr <= !req_in_range;
              acc     <= 2'd0;
              state   <= ST_IDLE;

              if (req_write) begin
                if (req_in_range) begin
                  regfile[req_addr] <= req_wdata;
                end
              end else begin
                if (req_in_range) begin
                  prdata <= regfile[req_addr];
                end
              end
            end else begin
              acc   <= acc + 2'd1;
              state <= ST_ACCESS;
            end
          end else if (psel && !penable) begin
            req_write <= pwrite;
            req_addr  <= paddr;
            req_wdata <= pwdata;
            acc       <= 2'd0;
            state     <= ST_ACCESS;
          end else begin
            acc   <= 2'd0;
            state <= ST_IDLE;
          end
        end

        default: begin
          acc   <= 2'd0;
          state <= ST_IDLE;
        end
      endcase
    end
  end

endmodule : apb_slave

Chunk ID: 74065d
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Output:
warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- package apb_pkg declared here: rtl/apb_pkg.sv:15

Chunk ID: e7e969
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Output:
PASS

Chunk ID: fa8e3c
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Output:
    35	    input  logic [AW-1:0]         paddr,
    36	    input  logic [DW-1:0]         pwdata,
    37	    output logic                  pready,
    38	    output logic [DW-1:0]         prdata,
    39	    output logic                  pslverr
    40	);
    41	
    42	  // ---------------------------------------------------------------------------
    43	  // State registers (provided). Add whatever combinational helpers you need.
    44	  // ---------------------------------------------------------------------------
    45	  logic [DW-1:0] regfile [0:NREG-1];
    46	  logic [1:0]    state;
    47	  logic [1:0]    acc;        // access-edge counter
    48	  logic          req_write;
    49	  logic [AW-1:0] req_addr;
    50	  logic [DW-1:0] req_wdata;
    51	  integer        i;
    52	
    53	  localparam logic [1:0] ST_IDLE   = 2'd0;
    54	  localparam logic [1:0] ST_ACCESS = 2'd1;
    55	
    56	  logic complete_now;
    57	  logic req_in_range;
    58	
    59	  assign complete_now = req_write ? (acc == 2'd2) : (acc == 2'd1);
    60	  assign req_in_range = (req_addr < NREG);
    61	
    62	  // Latch each setup phase, then count access-phase edges until the
    63	  // direction-dependent completion cycle.
    64	  always_ff @(posedge pclk or negedge presetn) begin
    65	    if (!presetn) begin
    66	      for (i = 0; i < NREG; i = i + 1) regfile[i] <= {DW{1'b0}};
    67	      state     <= ST_IDLE;
    68	      acc       <= 2'd0;
    69	      req_write <= 1'b0;
    70	      req_addr  <= {AW{1'b0}};
    71	      req_wdata <= {DW{1'b0}};
    72	      pready    <= 1'b0;
    73	      prdata    <= {DW{1'b0}};
    74	      pslverr   <= 1'b0;
    75	    end else begin
    76	      pready  <= 1'b0;
    77	      prdata  <= {DW{1'b0}};
    78	      pslverr <= 1'b0;
    79	
    80	      case (state)
    81	        ST_IDLE: begin
    82	          acc <= 2'd0;
    83	
    84	          if (psel && !penable) begin
    85	            req_write <= pwrite;
    86	            req_addr  <= paddr;
    87	            req_wdata <= pwdata;
    88	            state     <= ST_ACCESS;
    89	          end else begin
    90	            state <= ST_IDLE;
    91	          end
    92	        end
    93	
    94	        ST_ACCESS: begin
    95	          if (psel && penable) begin
    96	            if (complete_now) begin
    97	              pready  <= 1'b1;
    98	              pslverr <= !req_in_range;
    99	              acc     <= 2'd0;
   100	              state   <= ST_IDLE;
   101	
   102	              if (req_write) begin
   103	                if (req_in_range) begin
   104	                  regfile[req_addr] <= req_wdata;
   105	                end
   106	              end else begin
   107	                if (req_in_range) begin
   108	                  prdata <= regfile[req_addr];
   109	                end
   110	              end
   111	            end else begin
   112	              acc   <= acc + 2'd1;
   113	              state <= ST_ACCESS;
   114	            end
   115	          end else if (psel && !penable) begin
   116	            req_write <= pwrite;
   117	            req_addr  <= paddr;
   118	            req_wdata <= pwdata;
   119	            acc       <= 2'd0;
   120	            state     <= ST_ACCESS;
   121	          end else begin
   122	            acc   <= 2'd0;
   123	            state <= ST_IDLE;
   124	          end
   125	        end
   126	
   127	        default: begin
   128	          acc   <= 2'd0;
   129	          state <= ST_IDLE;
   130	        end
   131	      endcase
   132	    end
   133	  end
   134	
   135	endmodule : apb_slave