Wait-state register-file completer

Chunk ID: b2b1ab
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 19
Output:
apb_core/rtl/apb_slave.sv
apb_core/rtl/apb_pkg.sv
apb_core/rtl/apb_top.sv

Chunk ID: 552370
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Process exited with code 2
Original token count: 15
Output:
sed: can't read rtl/apb_slave.sv: No such file or directory

Chunk ID: 719ce7
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Output:
./apb_core/rtl/apb_top.sv
./apb_core/rtl/apb_pkg.sv
./apb_core/rtl/apb_slave.sv

Chunk ID: 2182e1
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 821
Output:
//==============================================================================
// apb_slave.sv
//
// Wait-state register-file completer for a two-phase select/enable handshake.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and the state registers are provided. The
//  handshake control, the wait-cycle counting, the register file commit and
//  the outputs are left as a TODO and currently drive constant zeros, so the
//  completer never raises pready and the verifier FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the
//  module name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module apb_slave #(
    parameter AW   = 6,
    parameter DW   = 32,
    parameter NREG = 16
) (
    input  logic                  pclk,
    input  logic                  presetn,
    input  logic                  psel,
    input  logic                  penable,
    input  logic                  pwrite,
    input  logic [AW-1:0]         paddr,
    input  logic [DW-1:0]         pwdata,
    output logic                  pready,
    output logic [DW-1:0]         prdata,
    output logic                  pslverr
);

  // ---------------------------------------------------------------------------
  // State registers (provided). Add whatever combinational helpers you need.
  // ---------------------------------------------------------------------------
  logic [DW-1:0] regfile [0:NREG-1];
  logic [1:0]    state;
  logic [1:0]    acc;        // access-edge counter
  integer        i;

  // ===========================================================================
  // TODO: IMPLEMENT THE COMPLETER.
  //   * walk the two-phase handshake (setup for one clk, then access);
  //   * insert the required number of wait cycles before completing, and pulse
  //     pready for exactly the completion clk;
  //   * commit a write / drive a read on the completion clk per instruction.md;
  //   * flag out-of-range accesses on the completion clk with no register effect;
  //   * presetn is asynchronous, active low, and clears the file and outputs.
  //
  // The placeholder below keeps the module compilable but INCORRECT.
  // ===========================================================================
  always_ff @(posedge pclk or negedge presetn) begin
    if (!presetn) begin
      for (i = 0; i < NREG; i = i + 1) regfile[i] <= {DW{1'b0}};
      state <= 2'd0;
      acc   <= 2'd0;
    end else begin
      // TODO: replace with the real handshake + datapath.
      state <= state;
      acc   <= acc;
    end
  end

  // TODO: replace these placeholder outputs with the real ones.
  assign pready  = 1'b0;
  assign prdata  = {DW{1'b0}};
  assign pslverr = 1'b0;

endmodule : apb_slave

Chunk ID: 330e71
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 209
Output:
//==============================================================================
// apb_pkg.sv
//
// Shared geometry for the wait-state register completer. The block exposes a
// register file of NREG words, each DW bits wide, addressed by an AW-bit word
// address. Parameters are declared without an explicit data type for broad
// simulator compatibility (Icarus Verilog 11); they default to integer
// constants, which is sufficient here.
//
// DO NOT change this file.
//==============================================================================
`ifndef APB_PKG_SV
`define APB_PKG_SV

package apb_pkg;

  localparam AW   = 6;    // address width (word address)
  localparam DW   = 32;   // data word width
  localparam NREG = 16;   // number of in-range registers (addr 0..NREG-1)

endpackage : apb_pkg

`endif // APB_PKG_SV

Chunk ID: a49b3e
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 363
Output:
//==============================================================================
// apb_top.sv
//
// Thin integration wrapper. The verification environment drives this wrapper so
// that the instantiation wiring is exercised alongside the completer itself. It
// instantiates apb_slave with the project-default geometry from apb_pkg.
//
// DO NOT change this file.
//==============================================================================
`timescale 1ns/1ps
`include "apb_pkg.sv"

module apb_top (
    input  logic                          pclk,
    input  logic                          presetn,
    input  logic                          psel,
    input  logic                          penable,
    input  logic                          pwrite,
    input  logic [apb_pkg::AW-1:0]        paddr,
    input  logic [apb_pkg::DW-1:0]        pwdata,
    output logic                          pready,
    output logic [apb_pkg::DW-1:0]        prdata,
    output logic                          pslverr
);

  // Bare instantiation: the completer carries its own default geometry, so a
  // submission needs no parameter override to elaborate correctly.
  apb_slave u_apb_slave (
      .pclk    (pclk),
      .presetn (presetn),
      .psel    (psel),
      .penable (penable),
      .pwrite  (pwrite),
      .paddr   (paddr),
      .pwdata  (pwdata),
      .pready  (pready),
      .prdata  (prdata),
      .pslverr (pslverr)
  );

endmodule : apb_top

Chunk ID: 8795bd
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 14
Output:
./rtl/apb_top.sv
./rtl/apb_pkg.sv
./rtl/apb_slave.sv

Chunk ID: e352a7
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 72
Output:
rtl/apb_top.sv:12: Include file apb_pkg.sv not found
warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- package apb_pkg declared here: rtl/apb_pkg.sv:15

Chunk ID: 005199
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Process exited with code 127
Original token count: 11
Output:
/bin/bash: line 1: git: command not found

Chunk ID: 0b349f
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 58
Output:
warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- package apb_pkg declared here: rtl/apb_pkg.sv:15

Chunk ID: 221333
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 1179
Output:
//==============================================================================
// apb_slave.sv
//
// Wait-state register-file completer for a two-phase select/enable handshake.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and the state registers are provided. The
//  handshake control, the wait-cycle counting, the register file commit and
//  the outputs are left as a TODO and currently drive constant zeros, so the
//  completer never raises pready and the verifier FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the
//  module name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module apb_slave #(
    parameter AW   = 6,
    parameter DW   = 32,
    parameter NREG = 16
) (
    input  logic                  pclk,
    input  logic                  presetn,
    input  logic                  psel,
    input  logic                  penable,
    input  logic                  pwrite,
    input  logic [AW-1:0]         paddr,
    input  logic [DW-1:0]         pwdata,
    output logic                  pready,
    output logic [DW-1:0]         prdata,
    output logic                  pslverr
);

  // ---------------------------------------------------------------------------
  // State registers (provided). Add whatever combinational helpers you need.
  // ---------------------------------------------------------------------------
  logic [DW-1:0] regfile [0:NREG-1];
  logic [1:0]    state;
  logic [1:0]    acc;        // access-edge counter
  logic          req_write;
  logic [AW-1:0] req_addr;
  logic [DW-1:0] req_wdata;
  integer        i;

  localparam [1:0] ST_IDLE   = 2'd0;
  localparam [1:0] ST_ACCESS = 2'd1;

  // ===========================================================================
  // TODO: IMPLEMENT THE COMPLETER.
  //   * walk the two-phase handshake (setup for one clk, then access);
  //   * insert the required number of wait cycles before completing, and pulse
  //     pready for exactly the completion clk;
  //   * commit a write / drive a read on the completion clk per instruction.md;
  //   * flag out-of-range accesses on the completion clk with no register effect;
  //   * presetn is asynchronous, active low, and clears the file and outputs.
  //
  // The placeholder below keeps the module compilable but INCORRECT.
  // ===========================================================================
  always_ff @(posedge pclk or negedge presetn) begin
    if (!presetn) begin
      for (i = 0; i < NREG; i = i + 1) regfile[i] <= {DW{1'b0}};
      state     <= ST_IDLE;
      acc       <= 2'd0;
      req_write <= 1'b0;
      req_addr  <= {AW{1'b0}};
      req_wdata <= {DW{1'b0}};
      pready    <= 1'b0;
      prdata    <= {DW{1'b0}};
      pslverr   <= 1'b0;
    end else begin
      pready  <= 1'b0;
      prdata  <= {DW{1'b0}};
      pslverr <= 1'b0;

      case (state)
        ST_IDLE: begin
          acc <= 2'd0;

          if (psel && !penable) begin
            req_write <= pwrite;
            req_addr  <= paddr;
            req_wdata <= pwdata;
            state     <= ST_ACCESS;
          end
        end

        ST_ACCESS: begin
          if (psel && penable) begin
            if (acc == (req_write ? 2'd2 : 2'd1)) begin
              pready  <= 1'b1;
              pslverr <= (req_addr >= NREG[AW-1:0]);

              if (req_addr < NREG[AW-1:0]) begin
                if (req_write) begin
                  regfile[req_addr] <= req_wdata;
                end else begin
                  prdata <= regfile[req_addr];
                end
              end

              state <= ST_IDLE;
              acc   <= 2'd0;
            end else begin
              acc <= acc + 2'd1;
            end
          end else begin
            state <= ST_IDLE;
            acc   <= 2'd0;

            if (psel && !penable) begin
              req_write <= pwrite;
              req_addr  <= paddr;
              req_wdata <= pwdata;
              state     <= ST_ACCESS;
            end
          end
        end

        default: begin
          state <= ST_IDLE;
          acc   <= 2'd0;
        end
      endcase
    end
  end

endmodule : apb_slave

Chunk ID: b85fb1
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 58
Output:
warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- package apb_pkg declared here: rtl/apb_pkg.sv:15

Chunk ID: 31b9cd
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 1415
Output:
     1	//==============================================================================
     2	// apb_slave.sv
     3	//
     4	// Wait-state register-file completer for a two-phase select/enable handshake.
     5	//
     6	// ---------------------------------------------------------------------------
     7	//  >>> IMPLEMENTATION REQUIRED <<<
     8	//
     9	//  The module ports, parameters and the state registers are provided. The
    10	//  handshake control, the wait-cycle counting, the register file commit and
    11	//  the outputs are left as a TODO and currently drive constant zeros, so the
    12	//  completer never raises pready and the verifier FAILS.
    13	//
    14	//  Implement the behaviour described in instruction.md. Do NOT change the
    15	//  module name, the port list, or the parameter list.
    16	//
    17	//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
    18	//  function-call result) is a syntax error under `iverilog -g2012`. Index only
    19	//  named signals, and do any bit work that needs an intermediate value inside a
    20	//  `function automatic` using named locals.
    21	// ---------------------------------------------------------------------------
    22	//==============================================================================
    23	`timescale 1ns/1ps
    24	
    25	module apb_slave #(
    26	    parameter AW   = 6,
    27	    parameter DW   = 32,
    28	    parameter NREG = 16
    29	) (
    30	    input  logic                  pclk,
    31	    input  logic                  presetn,
    32	    input  logic                  psel,
    33	    input  logic                  penable,
    34	    input  logic                  pwrite,
    35	    input  logic [AW-1:0]         paddr,
    36	    input  logic [DW-1:0]         pwdata,
    37	    output logic                  pready,
    38	    output logic [DW-1:0]         prdata,
    39	    output logic                  pslverr
    40	);
    41	
    42	  // ---------------------------------------------------------------------------
    43	  // State registers (provided). Add whatever combinational helpers you need.
    44	  // ---------------------------------------------------------------------------
    45	  logic [DW-1:0] regfile [0:NREG-1];
    46	  logic [1:0]    state;
    47	  logic [1:0]    acc;        // access-edge counter
    48	  logic          req_write;
    49	  logic [AW-1:0] req_addr;
    50	  logic [DW-1:0] req_wdata;
    51	  integer        i;
    52	
    53	  localparam [1:0] ST_IDLE   = 2'd0;
    54	  localparam [1:0] ST_ACCESS = 2'd1;
    55	
    56	  // ===========================================================================
    57	  // TODO: IMPLEMENT THE COMPLETER.
    58	  //   * walk the two-phase handshake (setup for one clk, then access);
    59	  //   * insert the required number of wait cycles before completing, and pulse
    60	  //     pready for exactly the completion clk;
    61	  //   * commit a write / drive a read on the completion clk per instruction.md;
    62	  //   * flag out-of-range accesses on the completion clk with no register effect;
    63	  //   * presetn is asynchronous, active low, and clears the file and outputs.
    64	  //
    65	  // The placeholder below keeps the module compilable but INCORRECT.
    66	  // ===========================================================================
    67	  always_ff @(posedge pclk or negedge presetn) begin
    68	    if (!presetn) begin
    69	      for (i = 0; i < NREG; i = i + 1) regfile[i] <= {DW{1'b0}};
    70	      state     <= ST_IDLE;
    71	      acc       <= 2'd0;
    72	      req_write <= 1'b0;
    73	      req_addr  <= {AW{1'b0}};
    74	      req_wdata <= {DW{1'b0}};
    75	      pready    <= 1'b0;
    76	      prdata    <= {DW{1'b0}};
    77	      pslverr   <= 1'b0;
    78	    end else begin
    79	      pready  <= 1'b0;
    80	      prdata  <= {DW{1'b0}};
    81	      pslverr <= 1'b0;
    82	
    83	      case (state)
    84	        ST_IDLE: begin
    85	          acc <= 2'd0;
    86	
    87	          if (psel && !penable) begin
    88	            req_write <= pwrite;
    89	            req_addr  <= paddr;
    90	            req_wdata <= pwdata;
    91	            state     <= ST_ACCESS;
    92	          end
    93	        end
    94	
    95	        ST_ACCESS: begin
    96	          if (psel && penable) begin
    97	            if (acc == (req_write ? 2'd2 : 2'd1)) begin
    98	              pready  <= 1'b1;
    99	              pslverr <= (req_addr >= NREG[AW-1:0]);
   100	
   101	              if (req_addr < NREG[AW-1:0]) begin
   102	                if (req_write) begin
   103	                  regfile[req_addr] <= req_wdata;
   104	                end else begin
   105	                  prdata <= regfile[req_addr];
   106	                end
   107	              end
   108	
   109	              state <= ST_IDLE;
   110	              acc   <= 2'd0;
   111	            end else begin
   112	              acc <= acc + 2'd1;
   113	            end
   114	          end else begin
   115	            state <= ST_IDLE;
   116	            acc   <= 2'd0;
   117	
   118	            if (psel && !penable) begin
   119	              req_write <= pwrite;
   120	              req_addr  <= paddr;
   121	              req_wdata <= pwdata;
   122	              state     <= ST_ACCESS;
   123	            end
   124	          end
   125	        end
   126	
   127	        default: begin
   128	          state <= ST_IDLE;
   129	          acc   <= 2'd0;
   130	        end
   131	      endcase
   132	    end
   133	  end
   134	
   135	endmodule : apb_slave

Chunk ID: a3eb2d
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 58
Output:
warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- package apb_pkg declared here: rtl/apb_pkg.sv:15

Chunk ID: 493af7
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 58
Output:
warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- package apb_pkg declared here: rtl/apb_pkg.sv:15

Chunk ID: 4d4f51
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 1120
Output:
     1	//==============================================================================
     2	// apb_slave.sv
     3	//
     4	// Wait-state register-file completer for a two-phase select/enable handshake.
     5	//
     6	// ---------------------------------------------------------------------------
     7	//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
     8	//  function-call result) is a syntax error under `iverilog -g2012`. Index only
     9	//  named signals, and do any bit work that needs an intermediate value inside a
    10	//  `function automatic` using named locals.
    11	// ---------------------------------------------------------------------------
    12	//==============================================================================
    13	`timescale 1ns/1ps
    14	
    15	module apb_slave #(
    16	    parameter AW   = 6,
    17	    parameter DW   = 32,
    18	    parameter NREG = 16
    19	) (
    20	    input  logic                  pclk,
    21	    input  logic                  presetn,
    22	    input  logic                  psel,
    23	    input  logic                  penable,
    24	    input  logic                  pwrite,
    25	    input  logic [AW-1:0]         paddr,
    26	    input  logic [DW-1:0]         pwdata,
    27	    output logic                  pready,
    28	    output logic [DW-1:0]         prdata,
    29	    output logic                  pslverr
    30	);
    31	
    32	  // ---------------------------------------------------------------------------
    33	  // State registers (provided). Add whatever combinational helpers you need.
    34	  // ---------------------------------------------------------------------------
    35	  logic [DW-1:0] regfile [0:NREG-1];
    36	  logic [1:0]    state;
    37	  logic [1:0]    acc;        // access-edge counter
    38	  logic          req_write;
    39	  logic [AW-1:0] req_addr;
    40	  logic [DW-1:0] req_wdata;
    41	  integer        i;
    42	
    43	  localparam [1:0] ST_IDLE   = 2'd0;
    44	  localparam [1:0] ST_ACCESS = 2'd1;
    45	
    46	  function automatic logic addr_in_range(input logic [AW-1:0] addr);
    47	    addr_in_range = (addr < NREG);
    48	  endfunction
    49	
    50	  always_ff @(posedge pclk or negedge presetn) begin
    51	    if (!presetn) begin
    52	      for (i = 0; i < NREG; i = i + 1) regfile[i] <= {DW{1'b0}};
    53	      state     <= ST_IDLE;
    54	      acc       <= 2'd0;
    55	      req_write <= 1'b0;
    56	      req_addr  <= {AW{1'b0}};
    57	      req_wdata <= {DW{1'b0}};
    58	      pready    <= 1'b0;
    59	      prdata    <= {DW{1'b0}};
    60	      pslverr   <= 1'b0;
    61	    end else begin
    62	      pready  <= 1'b0;
    63	      prdata  <= {DW{1'b0}};
    64	      pslverr <= 1'b0;
    65	
    66	      case (state)
    67	        ST_IDLE: begin
    68	          acc <= 2'd0;
    69	
    70	          if (psel && !penable) begin
    71	            req_write <= pwrite;
    72	            req_addr  <= paddr;
    73	            req_wdata <= pwdata;
    74	            state     <= ST_ACCESS;
    75	          end
    76	        end
    77	
    78	        ST_ACCESS: begin
    79	          if (psel && penable) begin
    80	            if (acc == (req_write ? 2'd2 : 2'd1)) begin
    81	              pready  <= 1'b1;
    82	              pslverr <= !addr_in_range(req_addr);
    83	
    84	              if (addr_in_range(req_addr)) begin
    85	                if (req_write) begin
    86	                  regfile[req_addr] <= req_wdata;
    87	                end else begin
    88	                  prdata <= regfile[req_addr];
    89	                end
    90	              end
    91	
    92	              state <= ST_IDLE;
    93	              acc   <= 2'd0;
    94	            end else begin
    95	              acc <= acc + 2'd1;
    96	            end
    97	          end else begin
    98	            state <= ST_IDLE;
    99	            acc   <= 2'd0;
   100	
   101	            if (psel && !penable) begin
   102	              req_write <= pwrite;
   103	              req_addr  <= paddr;
   104	              req_wdata <= pwdata;
   105	              state     <= ST_ACCESS;
   106	            end
   107	          end
   108	        end
   109	
   110	        default: begin
   111	          state <= ST_IDLE;
   112	          acc   <= 2'd0;
   113	        end
   114	      endcase
   115	    end
   116	  end
   117	
   118	endmodule : apb_slave