debug-halt-step-fsm

module TopModule (
  input  logic       clk,
  input  logic       rst,
  input  logic       halt_req_i,
  input  logic       resume_req_i,
  input  logic       step_req_i,
  input  logic       dbus_ren_i,
  input  logic [1:0] dbus_addr_i,
  output logic [7:0] dbus_rdata_o,
  output logic       halted_o,
  output logic       fetch_o
);

  typedef enum logic [1:0] {RUN, HALT1, HALTED, STEP1} state_t;
  state_t state, next_state;

  // Next-state logic
  always_comb begin
    next_state = state;
    unique case (state)
      RUN:    next_state = halt_req_i ? HALT1 : RUN;
      HALT1:  next_state = HALTED;                    // one extra fetch cycle, then halt
      HALTED: begin
        if (resume_req_i)                   next_state = RUN;
        else if (step_req_i && !halt_req_i) next_state = STEP1;
        else                                next_state = HALTED;
      end
      STEP1:  next_state = HALTED;                    // single fetch, back to halt
    endcase
  end

  // Registered-output decode (Moore decode of the *next* state, since outputs are flops)
  function automatic logic decode_fetch(state_t s);
    return (s == RUN) || (s == HALT1) || (s == STEP1);
  endfunction

  function automatic logic decode_halted(state_t s);
    return (s == HALTED);
  endfunction

  // Debug-port ROM
  function automatic logic [7:0] rom(logic [1:0] a);
    unique case (a)
      2'd0: rom = 8'h5A;
      2'd1: rom = 8'hC3;
      2'd2: rom = 8'h0F;
      2'd3: rom = 8'h96;
    endcase
  endfunction

  always_ff @(posedge clk) begin
    if (rst) begin
      state        <= RUN;
      fetch_o      <= 1'b0;
      halted_o     <= 1'b0;
      dbus_rdata_o <= 8'b0;
    end else begin
      state    <= next_state;
      fetch_o  <= decode_fetch(next_state);
      halted_o <= decode_halted(next_state);
      if (dbus_ren_i)
        dbus_rdata_o <= rom(dbus_addr_i);   // holds previous value while ren low
    end
  end

endmodule