apb-lite-slave-regfile

module TopModule(
    input             clk,
    input             rst,
    input             psel,
    input             penable,
    input             pwrite,
    input      [3:0]  paddr,
    input      [31:0] pwdata,
    output reg [31:0] prdata,
    output reg        pready,
    output reg        pslverr
);

    // Writable registers
    reg [31:0] word0;
    reg [7:0]  word1_low;
    reg [31:0] word3;

    // Tracks that the first (wait) access cycle of a held word-3
    // transaction has already elapsed.
    reg        w3_ready;

    wire access = psel && penable;
    wire offmap = (paddr >= 4'd4);

    // ---------------------------------------------------------------
    // Combinational APB response
    // ---------------------------------------------------------------
    always @(*) begin
        prdata  = 32'd0;
        pready  = 1'b0;
        pslverr = 1'b0;
        if (!rst && access) begin
            if (offmap) begin
                pready  = 1'b1;
                pslverr = 1'b1;
                prdata  = 32'd0;
            end else begin
                pslverr = 1'b0;
                case (paddr[1:0])
                    2'd0: begin
                        pready = 1'b1;
                        if (!pwrite) prdata = word0;
                    end
                    2'd1: begin
                        pready = 1'b1;
                        if (!pwrite) prdata = {24'd0, word1_low};
                    end
                    2'd2: begin
                        pready = 1'b1;
                        if (!pwrite) prdata = 32'h0AB15001;
                    end
                    2'd3: begin
                        pready = w3_ready;        // first access cycle waits
                        if (!pwrite) prdata = word3;
                    end
                endcase
            end
        end
    end

    // ---------------------------------------------------------------
    // Sequential state
    // ---------------------------------------------------------------
    always @(posedge clk) begin
        if (rst) begin
            word0     <= 32'd0;
            word1_low <= 8'd0;
            word3     <= 32'd0;
            w3_ready  <= 1'b0;
        end else begin
            // Word-3 wait-state tracking: set after the first access
            // cycle, cleared when the access phase ends or address moves.
            w3_ready <= (access && (paddr == 4'd3)) ? 1'b1 : 1'b0;

            // Register updates occur only on an accepted, error-free
            // write access cycle.
            if (access && pready && !pslverr && pwrite && !offmap) begin
                case (paddr[1:0])
                    2'd0: word0     <= pwdata;
                    2'd1: word1_low <= pwdata[7:0];
                    2'd2: ;               // read-only: write ignored
                    2'd3: word3     <= pwdata;
                endcase
            end
        end
    end

endmodule