serial-break-resync

// UART receiver.  Recovers bytes from a line idling high:
//   one low start bit, 8 data bits LSB-first, one high stop bit,
//   each BITLEN clock cycles.  All outputs registered.
module TopModule #(
    parameter int BITLEN = 16
)(
    input  logic       clk,
    input  logic       rst,
    input  logic       rx_i,
    output logic [7:0] data_o,
    output logic       valid_o,
    output logic       frame_err_o,
    output logic       break_o
);
    localparam int SIX  = 6*BITLEN;      // break threshold (six low bit periods)
    localparam int HALF = BITLEN/2;      // half a bit period, floored
    localparam int CW   = $clog2(SIX+1);
    localparam int BW   = $clog2(BITLEN+1);

    localparam logic [1:0] S_IDLE  = 2'd0,
                           S_DATA  = 2'd1,
                           S_BREAK = 2'd2, // break asserted, waiting for line high
                           S_RECOV = 2'd3;  // waiting for six continuous high periods

    logic          rx_meta, rx_sync;   // two-flop synchronizer
    logic [1:0]    state;
    logic [CW-1:0] low_cnt, high_cnt;
    logic [BW-1:0] cnt;                 // cycles since last sample point
    logic [3:0]    data_idx;            // data bits sampled so far (0..8; 8 => stop)
    logic [3:0]    d_pending;           // bytes still forced to frame_err
    logic [7:0]    shiftreg;
    logic [CW-1:0] nlow;                // this cycle's consecutive-low count

    always_ff @(posedge clk) begin
        // synchronizer (default)
        rx_meta <= rx_i;
        rx_sync <= rx_meta;

        // one-cycle pulses default low
        valid_o     <= 1'b0;
        frame_err_o <= 1'b0;

        if (rst) begin
            rx_meta     <= 1'b1;
            rx_sync     <= 1'b1;
            state       <= S_IDLE;
            low_cnt     <= '0;
            high_cnt    <= '0;
            cnt         <= '0;
            data_idx    <= '0;
            d_pending   <= '0;
            shiftreg    <= '0;
            data_o      <= '0;
            valid_o     <= 1'b0;
            frame_err_o <= 1'b0;
            break_o     <= 1'b0;
        end else begin
            // consecutive-low counter, measured from the high->low edge
            nlow = (rx_sync == 1'b0)
                     ? ((low_cnt >= CW'(SIX)) ? CW'(SIX) : low_cnt + 1'b1)
                     : '0;
            low_cnt <= nlow;

            if ((state == S_IDLE || state == S_DATA) && (nlow >= CW'(SIX))) begin
                // Break preempts any in-progress frame: byte dropped, no valid.
                break_o   <= 1'b1;
                d_pending <= (state == S_DATA) ? data_idx : 4'd0;  // d, zero if none
                state     <= S_BREAK;
            end else begin
                case (state)
                    S_IDLE: begin
                        // Accept a start the exact cycle a fresh low reaches HALF.
                        if (rx_sync == 1'b0 && nlow == CW'(HALF)) begin
                            state    <= S_DATA;
                            cnt      <= '0;
                            data_idx <= '0;
                            shiftreg <= '0;
                        end
                    end

                    S_DATA: begin
                        if (cnt == BW'(BITLEN-1)) begin
                            cnt <= '0;
                            if (data_idx < 4'd8) begin
                                shiftreg[data_idx] <= rx_sync;   // LSB first
                                data_idx <= data_idx + 1'b1;
                            end else begin
                                // stop bit sampled -> deliver byte
                                valid_o     <= 1'b1;
                                data_o      <= shiftreg;
                                frame_err_o <= (d_pending != 4'd0) || (rx_sync == 1'b0);
                                if (d_pending != 4'd0)
                                    d_pending <= d_pending - 1'b1;
                                state <= S_IDLE;
                            end
                        end else begin
                            cnt <= cnt + 1'b1;
                        end
                    end

                    S_BREAK: begin
                        if (rx_sync == 1'b1) begin
                            break_o  <= 1'b0;        // break falls when line high again
                            high_cnt <= CW'(1);      // this high cycle counts
                            state    <= S_RECOV;
                        end
                    end

                    S_RECOV: begin
                        // Re-arm only after six continuous high periods; any low
                        // restarts the count, break stays low.
                        if (rx_sync == 1'b1) begin
                            if (high_cnt + 1'b1 >= CW'(SIX))
                                state <= S_IDLE;
                            else
                                high_cnt <= high_cnt + 1'b1;
                        end else begin
                            high_cnt <= '0;
                        end
                    end

                    default: state <= S_IDLE;
                endcase
            end
        end
    end
endmodule