stream-frame-hold

module TopModule (
    input  wire        clk,
    input  wire        rst,
    input  wire        wr_i,
    input  wire [31:0] wr_data,
    input  wire        wr_last_i,
    output wire        wr_ready_o,
    output reg         m_tvalid_o,
    output reg  [31:0] m_tdata_o,
    output reg         m_tlast_o,
    input  wire        m_tready_i
);

    // Depth-8 FIFO holding {last, data}
    reg [32:0] mem [0:7];
    reg [2:0]  wr_ptr;
    reg [2:0]  rd_ptr;
    reg [3:0]  count;

    wire fifo_full  = (count == 4'd8);
    wire fifo_empty = (count == 4'd0);

    assign wr_ready_o = !fifo_full;

    // Output-side control
    reg [1:0]  pad_pending;   // number of pad beats still to emit
    reg [31:0] last_payload;  // data of most recent wr_last payload
    reg        cur_last;      // loaded beat is a payload with last=1

    // Event decisions
    wire do_push     = wr_i && wr_ready_o;
    wire load_en     = !m_tvalid_o;                       // may load when idle
    wire do_pad_load = load_en && (pad_pending != 2'd0);
    wire do_fifo_load= load_en && (pad_pending == 2'd0) && !fifo_empty;
    wire do_pop      = do_fifo_load;

    always @(posedge clk) begin
        if (rst) begin
            m_tvalid_o   <= 1'b0;
            m_tdata_o    <= 32'b0;
            m_tlast_o    <= 1'b0;
            pad_pending  <= 2'd0;
            last_payload <= 32'b0;
            cur_last     <= 1'b0;
            wr_ptr       <= 3'd0;
            rd_ptr       <= 3'd0;
            count        <= 4'd0;
        end else begin
            // FIFO write / read pointers
            if (do_push) begin
                mem[wr_ptr] <= {wr_last_i, wr_data};
                wr_ptr      <= wr_ptr + 3'd1;
            end
            if (do_pop) begin
                rd_ptr <= rd_ptr + 3'd1;
            end
            // Occupancy updated once for both push and pop
            count <= count + do_push - do_pop;

            // Output stream (registered)
            if (m_tvalid_o) begin
                if (m_tready_i) begin
                    // xfer edge: deassert valid (one idle cycle enforced)
                    m_tvalid_o <= 1'b0;
                    if (cur_last) begin
                        // payload with last accepted -> queue 2 pads
                        pad_pending  <= 2'd2;
                        last_payload <= m_tdata_o;
                    end
                end
                // while m_tready_i==0 hold the beat unchanged
            end else begin
                // idle: load next beat, pads take priority
                if (do_pad_load) begin
                    m_tvalid_o  <= 1'b1;
                    m_tdata_o   <= last_payload ^ 32'h0BADF00D;
                    m_tlast_o   <= (pad_pending == 2'd1); // last only on 2nd pad
                    cur_last    <= 1'b0;                  // pads don't retrigger
                    pad_pending <= pad_pending - 2'd1;
                end else if (do_fifo_load) begin
                    m_tvalid_o <= 1'b1;
                    m_tdata_o  <= mem[rd_ptr][31:0];
                    m_tlast_o  <= 1'b0;                   // payload beats: tlast=0
                    cur_last   <= mem[rd_ptr][32];
                end
            end
        end
    end

endmodule