A bridge shares one read-only memory port between requesters A and B, keeping neither starved.
Ports: clk, rst, a_req_i, a_addr_i (8), a_ack_o, a_data_o (16), b_req_i, b_addr_i (8), b_ack_o, b_data_o (16), m_req_o, m_addr_o (8), m_data_i (16).
rst is synchronous active high, clearing all state and outputs to 0. All outputs are registered. A requester holds req and addr stable through the cycle after its ack.
The bridge samples on the idle edge after a request first appears, calling that edge E; a freshly-arriving request is registered one idle cycle before it is sampled as E. One request finishes before the next is sampled. m_req_o and m_addr_o carry the chosen command during E+1 only. m_data_i is valid during E+3. The winner's ack and word are high during E+4 only, the other ack 0. E+4 is the last occupied cycle; the bridge is idle again at E+5, never earlier or later.
A sample after a fully idle stretch favours A when both ask. The sample at E+5 directly after an operation instead takes the requester that did not just win if it asks, else the one that did; a later idle stretch resets this, so the next cold sample favours A again.
edge E E+1 E+3 E+4 E+5 E+6
m_req_o 0 1 0 0 0 1
a_ack_o 0 0 0 1 0 0
a_data_o and b_data_o matter only while the matching ack is high. Write module TopModule to /app/dut.sv. Plain ASCII synthesizable SystemVerilog only: no define, include, ifdef, system tasks, force, release, bind.