Instruction-retire commit handshake

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Output:
rtr_core/rtl/rtr_top.sv
rtr_core/rtl/rtr_pkg.sv
rtr_core/rtl/rtr.sv

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/bin/bash: line 1: git: command not found

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Output:
//==============================================================================
// rtr.sv
//
// Instruction-retire commit handshake.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and the state registers are provided. The
//  control FSM, the latency counter and the outputs are left as a TODO and
//  currently drive constant zeros, so the block never accepts or retires and
//  the verifier FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the
//  module name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module rtr #(
    parameter DW       = 8,
    parameter K        = 3,
    parameter TRAPCODE = 8'hEE
) (
    input  logic                clk,
    input  logic                rst_n,
    input  logic                req,
    input  logic [DW-1:0]       op,
    input  logic                trap,
    output logic                accept,
    output logic                busy,
    output logic                done,
    output logic [DW-1:0]       result
);

  // ---------------------------------------------------------------------------
  // State registers (provided). Use these (and add your own as needed) to track
  // where in a retire the block is and the payload captured at accept time.
  // ---------------------------------------------------------------------------
  logic [1:0]      phase;     // control state
  logic [DW-1:0]   latch;     // payload captured at accept
  logic [3:0]      cnt;       // latency counter

  // ===========================================================================
  // TODO: IMPLEMENT THE RETIRE HANDSHAKE.
  //   * accept a req only while ready; pulse accept for one clk and capture op;
  //   * drive busy, done and result with the disclosed latencies and values;
  //   * honour the trap pre-empt and the mandatory idle edge;
  //   * asynchronous active-low reset clears all state and outputs.
  //
  // The placeholder below keeps the module compilable but INCORRECT.
  // ===========================================================================
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      phase <= 2'd0;
      latch <= '0;
      cnt   <= '0;
    end else begin
      // TODO: replace with the real control + datapath.
      phase <= phase;
      latch <= latch;
      cnt   <= cnt;
    end
  end

  // TODO: replace these placeholder outputs with the real ones.
  assign accept = 1'b0;
  assign busy   = 1'b0;
  assign done   = 1'b0;
  assign result = '0;

endmodule : rtr

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Output:
//==============================================================================
// rtr_top.sv
//
// Thin integration wrapper. The verification environment drives this wrapper so
// that the instantiation wiring is exercised alongside the retire block itself.
// It instantiates rtr with the project-default geometry from rtr_pkg.
//
// DO NOT change this file.
//==============================================================================
`timescale 1ns/1ps
`include "rtr_pkg.sv"

module rtr_top (
    input  logic                            clk,
    input  logic                            rst_n,
    input  logic                            req,
    input  logic [rtr_pkg::DW-1:0]          op,
    input  logic                            trap,
    output logic                            accept,
    output logic                            busy,
    output logic                            done,
    output logic [rtr_pkg::DW-1:0]          result
);

  // Bare instantiation: the block carries its own default geometry, so a
  // submission needs no parameter override to elaborate correctly.
  rtr u_rtr (
      .clk    (clk),
      .rst_n  (rst_n),
      .req    (req),
      .op     (op),
      .trap   (trap),
      .accept (accept),
      .busy   (busy),
      .done   (done),
      .result (result)
  );

endmodule : rtr_top

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Output:
//==============================================================================
// rtr_pkg.sv
//
// Shared geometry for the instruction-retire commit handshake. The block latches
// an 8-bit payload at accept time, counts a fixed latency, and drives a one-cycle
// done strobe with either the latched payload or a masked trap code. Parameters
// are declared without an explicit data type for broad simulator compatibility
// (Icarus Verilog 11); they default to integer constants, which is sufficient
// here.
//
// DO NOT change this file.
//==============================================================================
`ifndef RTR_PKG_SV
`define RTR_PKG_SV

package rtr_pkg;

  localparam DW       = 8;        // payload word width
  localparam K        = 3;        // normal retire latency (accept -> done edges)
  localparam TRAPCODE = 8'hEE;    // masked payload driven on a trapped retire

endpackage : rtr_pkg

`endif // RTR_PKG_SV

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Output:
//==============================================================================
// rtr.sv
//
// Instruction-retire commit handshake.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and the state registers are provided. The
//  control FSM, the latency counter and the outputs are left as a TODO and
//  currently drive constant zeros, so the block never accepts or retires and
//  the verifier FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the
//  module name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module rtr #(
    parameter DW       = 8,
    parameter K        = 3,
    parameter TRAPCODE = 8'hEE
) (
    input  logic                clk,
    input  logic                rst_n,
    input  logic                req,
    input  logic [DW-1:0]       op,
    input  logic                trap,
    output logic                accept,
    output logic                busy,
    output logic                done,
    output logic [DW-1:0]       result
);

  // ---------------------------------------------------------------------------
  // State registers (provided). Use these (and add your own as needed) to track
  // where in a retire the block is and the payload captured at accept time.
  // ---------------------------------------------------------------------------
  logic [1:0]      phase;     // control state
  logic [DW-1:0]   latch;     // payload captured at accept
  logic [3:0]      cnt;       // latency counter

  localparam PH_IDLE = 2'd0;
  localparam PH_RUN  = 2'd1;
  localparam PH_REST = 2'd2;

  // ===========================================================================
  // TODO: IMPLEMENT THE RETIRE HANDSHAKE.
  //   * accept a req only while ready; pulse accept for one clk and capture op;
  //   * drive busy, done and result with the disclosed latencies and values;
  //   * honour the trap pre-empt and the mandatory idle edge;
  //   * asynchronous active-low reset clears all state and outputs.
  //
  // The placeholder below keeps the module compilable but INCORRECT.
  // ===========================================================================
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      phase  <= PH_IDLE;
      latch  <= '0;
      cnt    <= '0;
      accept <= 1'b0;
      busy   <= 1'b0;
      done   <= 1'b0;
      result <= '0;
    end else begin
      accept <= 1'b0;
      busy   <= 1'b0;
      done   <= 1'b0;
      result <= '0;

      case (phase)
        PH_IDLE: begin
          cnt <= '0;
          if (req) begin
            accept <= 1'b1;
            latch  <= op;
            cnt    <= 4'd1;
            phase  <= PH_RUN;
          end
        end

        PH_RUN: begin
          if (cnt >= K) begin
            done   <= 1'b1;
            result <= latch;
            cnt    <= '0;
            phase  <= PH_REST;
          end else begin
            busy <= 1'b1;
            if (trap) begin
              latch <= TRAPCODE;
              cnt   <= K;
            end else begin
              cnt <= cnt + 4'd1;
            end
          end
        end

        PH_REST: begin
          cnt   <= '0;
          phase <= PH_IDLE;
        end

        default: begin
          phase <= PH_IDLE;
          cnt   <= '0;
          latch <= '0;
        end
      endcase
    end
  end

endmodule : rtr

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Output:
PASS

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PASS

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Output:
     1	//==============================================================================
     2	// rtr.sv
     3	//
     4	// Instruction-retire commit handshake.
     5	//
     6	// ---------------------------------------------------------------------------
     7	//  The module ports and parameters are fixed by the verification wrapper. The
     8	//  control below implements the accept, busy, done, trap, and rest-beat timing
     9	//  described in instruction.md.
    10	//
    11	//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
    12	//  function-call result) is a syntax error under `iverilog -g2012`. Index only
    13	//  named signals, and do any bit work that needs an intermediate value inside a
    14	//  `function automatic` using named locals.
    15	// ---------------------------------------------------------------------------
    16	//==============================================================================
    17	`timescale 1ns/1ps
    18	
    19	module rtr #(
    20	    parameter DW       = 8,
    21	    parameter K        = 3,
    22	    parameter TRAPCODE = 8'hEE
    23	) (
    24	    input  logic                clk,
    25	    input  logic                rst_n,
    26	    input  logic                req,
    27	    input  logic [DW-1:0]       op,
    28	    input  logic                trap,
    29	    output logic                accept,
    30	    output logic                busy,
    31	    output logic                done,
    32	    output logic [DW-1:0]       result
    33	);
    34	
    35	  // ---------------------------------------------------------------------------
    36	  // State registers (provided). Use these (and add your own as needed) to track
    37	  // where in a retire the block is and the payload captured at accept time.
    38	  // ---------------------------------------------------------------------------
    39	  logic [1:0]      phase;     // control state
    40	  logic [DW-1:0]   latch;     // payload captured at accept
    41	  logic [3:0]      cnt;       // latency counter
    42	
    43	  localparam PH_IDLE = 2'd0;
    44	  localparam PH_RUN  = 2'd1;
    45	  localparam PH_REST = 2'd2;
    46	
    47	  // ===========================================================================
    48	  // Retire handshake.
    49	  // ===========================================================================
    50	  always_ff @(posedge clk or negedge rst_n) begin
    51	    if (!rst_n) begin
    52	      phase  <= PH_IDLE;
    53	      latch  <= '0;
    54	      cnt    <= '0;
    55	      accept <= 1'b0;
    56	      busy   <= 1'b0;
    57	      done   <= 1'b0;
    58	      result <= '0;
    59	    end else begin
    60	      accept <= 1'b0;
    61	      busy   <= 1'b0;
    62	      done   <= 1'b0;
    63	      result <= '0;
    64	
    65	      case (phase)
    66	        PH_IDLE: begin
    67	          cnt <= '0;
    68	          if (req) begin
    69	            accept <= 1'b1;
    70	            latch  <= op;
    71	            cnt    <= 4'd1;
    72	            phase  <= PH_RUN;
    73	          end
    74	        end
    75	
    76	        PH_RUN: begin
    77	          if (cnt >= K) begin
    78	            done   <= 1'b1;
    79	            result <= latch;
    80	            cnt    <= '0;
    81	            phase  <= PH_REST;
    82	          end else begin
    83	            busy <= 1'b1;
    84	            if (trap) begin
    85	              latch <= TRAPCODE;
    86	              cnt   <= K;
    87	            end else begin
    88	              cnt <= cnt + 4'd1;
    89	            end
    90	          end
    91	        end
    92	
    93	        PH_REST: begin
    94	          cnt   <= '0;
    95	          phase <= PH_IDLE;
    96	        end
    97	
    98	        default: begin
    99	          phase <= PH_IDLE;
   100	          cnt   <= '0;
   101	          latch <= '0;
   102	        end
   103	      endcase
   104	    end
   105	  end
   106	
   107	endmodule : rtr