serial-break-resync

// UART receiver: recovers bytes from a line idling high.
// Frame: 1 low start bit, 8 data bits LSB-first, 1 high stop bit,
// each BITLEN clock cycles. All outputs are registered.
module TopModule #(
    parameter BITLEN = 4
) (
    input  logic       clk,
    input  logic       rst,
    input  logic       rx_i,
    output logic [7:0] data_o,
    output logic       valid_o,
    output logic       frame_err_o,
    output logic       break_o
);

    // Derived timing constants.
    localparam int HALF     = BITLEN/2;                 // floored half bit period
    localparam int STARTAT  = (HALF == 0) ? 1 : HALF;   // low cycles to accept a start
    localparam int BREAKLEN = 6*BITLEN;                 // six continuous low bit periods
    localparam int RECHIGH  = 6*BITLEN;                 // high needed to leave recovery
    localparam int CW       = $clog2(6*BITLEN + 2) + 2; // counter width

    // ----- two-flop synchronizer (idle high) -----
    logic sync0, rx;
    always_ff @(posedge clk) begin
        if (rst) begin
            sync0 <= 1'b1;
            rx    <= 1'b1;
        end else begin
            sync0 <= rx_i;
            rx    <= sync0;
        end
    end

    // Continuous low / high run lengths of the synchronized line (saturating).
    logic [CW-1:0] low_run, high_run;
    wire   [CW-1:0] lrn = (rx == 1'b0)
                          ? ((low_run  >= BREAKLEN[CW-1:0]) ? BREAKLEN[CW-1:0] : low_run  + 1'b1)
                          : '0;
    wire   [CW-1:0] hrn = (rx == 1'b1)
                          ? ((high_run >= RECHIGH[CW-1:0])  ? RECHIGH[CW-1:0]  : high_run + 1'b1)
                          : '0;

    // FSM.
    typedef enum logic [1:0] {IDLE, DATA, BRK, RECOVER} state_t;
    state_t state;

    logic [CW-1:0] frame_cnt;   // cycles since last sample point within a frame
    logic [3:0]    data_bits;   // data bits sampled so far in the current frame (0..8)
    logic [7:0]    shiftreg;    // assembled byte
    logic [3:0]    pend;        // pending forced-frame-error byte count (d)

    always_ff @(posedge clk) begin
        if (rst) begin
            state       <= IDLE;
            low_run     <= '0;
            high_run    <= '0;
            frame_cnt   <= '0;
            data_bits   <= '0;
            shiftreg    <= '0;
            pend        <= '0;
            data_o      <= '0;
            valid_o     <= 1'b0;
            frame_err_o <= 1'b0;
            break_o     <= 1'b0;
        end else begin
            // Global run counters and one-cycle output defaults.
            low_run     <= lrn;
            high_run    <= hrn;
            valid_o     <= 1'b0;
            frame_err_o <= 1'b0;
            // break_o and data_o retain their value unless updated below.

            // Break preempts any in-progress frame (only in normal operation).
            if ((state == IDLE || state == DATA) && lrn == BREAKLEN[CW-1:0]) begin
                break_o   <= 1'b1;
                pend      <= (state == DATA) ? data_bits : 4'd0; // d = data bits sampled
                state     <= BRK;
                frame_cnt <= '0;
                data_bits <= '0;                                 // drop the byte
            end else begin
                case (state)
                    IDLE: begin
                        // Accept a start once a fresh low reaches half a bit period.
                        if (lrn == STARTAT[CW-1:0]) begin
                            state     <= DATA;
                            frame_cnt <= '0;
                            data_bits <= '0;
                            shiftreg  <= '0;
                        end
                    end

                    DATA: begin
                        if (frame_cnt == (BITLEN-1)) begin
                            frame_cnt <= '0;
                            if (data_bits < 8) begin
                                // Sample a data bit at its center (LSB first).
                                shiftreg[data_bits[2:0]] <= rx;
                                data_bits <= data_bits + 1'b1;
                            end else begin
                                // Sample the stop bit: deliver the byte.
                                valid_o     <= 1'b1;
                                data_o      <= shiftreg;
                                frame_err_o <= (~rx) | (pend != 0);
                                if (pend != 0) pend <= pend - 1'b1;
                                data_bits   <= '0;
                                state       <= IDLE;
                            end
                        end else begin
                            frame_cnt <= frame_cnt + 1'b1;
                        end
                    end

                    BRK: begin
                        // Hold break high until the line returns high.
                        if (rx) begin
                            break_o <= 1'b0;
                            state   <= RECOVER;
                        end
                    end

                    RECOVER: begin
                        // Require six continuous high bit periods before rearming.
                        if (hrn == RECHIGH[CW-1:0])
                            state <= IDLE;
                    end

                    default: state <= IDLE;
                endcase
            end
        end
    end

endmodule