apb-lite-slave-regfile

module TopModule (
    input  wire        clk,
    input  wire        rst,
    input  wire        psel,
    input  wire        penable,
    input  wire        pwrite,
    input  wire [3:0]  paddr,
    input  wire [31:0] pwdata,
    output reg  [31:0] prdata,
    output reg         pready,
    output reg         pslverr
);

    // Writable registers
    reg [31:0] reg0;
    reg [7:0]  reg1_low;
    reg [31:0] reg3;

    // Word-3 wait tracking: 0 during the first access cycle of a held
    // transaction, 1 on every later access cycle of that same transaction.
    reg w3_waited;

    wire access = psel & penable;

    // Combinational outputs
    always @(*) begin
        prdata  = 32'd0;
        pready  = 1'b0;
        pslverr = 1'b0;

        if (!rst && access) begin
            if (paddr >= 4'd4) begin
                // Off-map: complete with error
                pready  = 1'b1;
                pslverr = 1'b1;
                prdata  = 32'd0;
            end else if (paddr == 4'd3) begin
                // Word 3: one wait access cycle
                pready  = w3_waited;
                pslverr = 1'b0;
                if (!pwrite)
                    prdata = reg3;
            end else begin
                // Words 0, 1, 2: complete on first access cycle
                pready  = 1'b1;
                pslverr = 1'b0;
                if (!pwrite) begin
                    case (paddr)
                        4'd0: prdata = reg0;
                        4'd1: prdata = {24'd0, reg1_low};
                        4'd2: prdata = 32'h0AB15001;
                        default: prdata = 32'd0;
                    endcase
                end
            end
        end
    end

    // Sequential state
    always @(posedge clk) begin
        if (rst) begin
            reg0      <= 32'd0;
            reg1_low  <= 8'd0;
            reg3      <= 32'd0;
            w3_waited <= 1'b0;
        end else begin
            // Track word-3 wait state
            if (access) begin
                if (paddr == 4'd3)
                    w3_waited <= 1'b1;  // set after the first access cycle
            end else begin
                w3_waited <= 1'b0;      // clear when transaction not in access
            end

            // Writes commit only on an access cycle that completes without error
            if (access && pready && !pslverr && pwrite) begin
                case (paddr)
                    4'd0: reg0     <= pwdata;
                    4'd1: reg1_low <= pwdata[7:0];
                    4'd2: ;                        // read-only: accepted, ignored
                    4'd3: reg3     <= pwdata;
                    default: ;                     // off-map: pslverr blocks this
                endcase
            end
        end
    end

endmodule