apb-lite-slave-regfile

module TopModule (
    input  wire        clk,
    input  wire        rst,
    input  wire        psel,
    input  wire        penable,
    input  wire        pwrite,
    input  wire [3:0]  paddr,
    input  wire [31:0] pwdata,
    output reg  [31:0] prdata,
    output reg         pready,
    output reg         pslverr
);

    // Writable registers
    reg [31:0] word0;
    reg [7:0]  word1;
    reg [31:0] word3;

    localparam [31:0] WORD2_CONST = 32'h0AB15001;

    // Tracks whether the current held transaction has already passed its
    // first access cycle (used to insert one wait cycle for word 3).
    reg waited;

    wire access  = psel & penable;
    wire off_map = paddr >= 4'd4;

    // Combinational APB response outputs
    always @(*) begin
        prdata  = 32'd0;
        pready  = 1'b0;
        pslverr = 1'b0;

        if (!rst && access) begin
            if (off_map) begin
                pready  = 1'b1;
                pslverr = 1'b1;
                prdata  = 32'd0;
            end else if (paddr == 4'd3) begin
                pready  = waited;          // one wait access cycle
                pslverr = 1'b0;
                if (!pwrite)
                    prdata = word3;
            end else begin
                pready  = 1'b1;
                pslverr = 1'b0;
                if (!pwrite) begin
                    case (paddr)
                        4'd0: prdata = word0;
                        4'd1: prdata = {24'd0, word1};
                        4'd2: prdata = WORD2_CONST;
                        default: prdata = 32'd0;
                    endcase
                end
            end
        end
    end

    // Wait-state tracking
    always @(posedge clk) begin
        if (rst)
            waited <= 1'b0;
        else if (!access)
            waited <= 1'b0;
        else
            waited <= 1'b1;
    end

    // Register writes: only on an access cycle with pready=1 and pslverr=0
    always @(posedge clk) begin
        if (rst) begin
            word0 <= 32'd0;
            word1 <= 8'd0;
            word3 <= 32'd0;
        end else if (access && pwrite && pready && !pslverr) begin
            case (paddr)
                4'd0: word0 <= pwdata;
                4'd1: word1 <= pwdata[7:0];
                4'd3: word3 <= pwdata;
                // word 2 write accepted but ignored; off-map excluded by pslverr
                default: ;
            endcase
        end
    end

endmodule