bus-slave-abort-ack

module TopModule(
  input clk,
  input rst,
  input cyc_i,
  input stb_i,
  input we_i,
  input [1:0] adr_i,
  input [15:0] dat_i,
  output reg stall_o,
  output reg ack_o,
  output reg [15:0] dat_o
);

  // four 16-bit slots and their primed bits
  reg [15:0] mem0, mem1, mem2, mem3;
  reg [3:0]  primed;

  // read pipeline: delay 2 (accept at E -> respond at E+2)
  reg        r1_v, r2_v;      // r1 fires this edge, r2 fires next+1
  reg [1:0]  r1_adr, r2_adr;
  reg [15:0] r1_val, r2_val;  // captured slot value at accept
  reg        r1_p, r2_p;      // captured primed bit

  // write pipeline: delay 3 (accept at E -> commit/respond at E+3)
  reg        w1_v, w2_v, w3_v;
  reg [1:0]  w1_adr, w2_adr, w3_adr;
  reg [15:0] w1_dat, w2_dat, w3_dat;

  // combinational working values
  reg        accept, is_read, is_write;
  reg        read_fires, write_fires;
  reg [15:0] cur_slot, new_slot, rd_data;
  reg [15:0] cap_val;
  reg        cap_p;

  // mix(a,x): pack into lane k the bit-reversed source lane (k+a)%4
  function [15:0] mix;
    input [1:0] a;
    input [15:0] x;
    integer k, i, j;
    begin
      mix = 16'b0;
      for (k = 0; k < 4; k = k + 1) begin
        j = (k + a) % 4;
        for (i = 0; i < 4; i = i + 1) begin
          mix[k + 4*i] = x[j + 4*(3-i)];
        end
      end
    end
  endfunction

  // read slot value / primed by index
  always @(*) begin
    case (adr_i)
      2'd0: cap_val = mem0;
      2'd1: cap_val = mem1;
      2'd2: cap_val = mem2;
      default: cap_val = mem3;
    endcase
    cap_p = primed[adr_i];
    case (w1_adr)
      2'd0: cur_slot = mem0;
      2'd1: cur_slot = mem1;
      2'd2: cur_slot = mem2;
      default: cur_slot = mem3;
    endcase
    // acceptance
    accept   = cyc_i & stb_i & ~stall_o;
    is_read  = accept & ~we_i;
    is_write = accept &  we_i;
    // responses firing this edge
    read_fires  = r1_v;
    write_fires = w1_v;
    // read response data
    if (r1_p) rd_data = mix(r1_adr, r1_val);
    else      rd_data = 16'b0;
    // committed write value
    new_slot = mix(w1_adr, cur_slot) ^ w1_dat;
  end

  always @(posedge clk) begin
    if (rst) begin
      mem0 <= 16'b0; mem1 <= 16'b0; mem2 <= 16'b0; mem3 <= 16'b0;
      primed <= 4'b0;
      r1_v <= 1'b0; r2_v <= 1'b0;
      r1_adr <= 2'b0; r2_adr <= 2'b0;
      r1_val <= 16'b0; r2_val <= 16'b0;
      r1_p <= 1'b0; r2_p <= 1'b0;
      w1_v <= 1'b0; w2_v <= 1'b0; w3_v <= 1'b0;
      w1_adr <= 2'b0; w2_adr <= 2'b0; w3_adr <= 2'b0;
      w1_dat <= 16'b0; w2_dat <= 16'b0; w3_dat <= 16'b0;
      stall_o <= 1'b0;
      ack_o <= 1'b0;
      dat_o <= 16'b0;
    end else begin
      // default outputs (0 outside active response edges)
      ack_o <= 1'b0;
      dat_o <= 16'b0;

      // commit a firing write regardless of cyc_i (dropped writes still commit)
      if (write_fires) begin
        case (w1_adr)
          2'd0: mem0 <= new_slot;
          2'd1: mem1 <= new_slot;
          2'd2: mem2 <= new_slot;
          default: mem3 <= new_slot;
        endcase
        primed[w1_adr] <= 1'b1;
      end

      // response: ack pulses only with cyc_i high; read data wins collisions
      if (cyc_i & (read_fires | write_fires)) begin
        ack_o <= 1'b1;
        if (read_fires) dat_o <= rd_data;
        else            dat_o <= new_slot;
      end

      // read pipeline shift
      r1_v   <= r2_v;
      r1_adr <= r2_adr;
      r1_val <= r2_val;
      r1_p   <= r2_p;
      r2_v   <= is_read;
      r2_adr <= adr_i;
      r2_val <= cap_val;
      r2_p   <= cap_p;

      // write pipeline shift
      w1_v   <= w2_v;
      w1_adr <= w2_adr;
      w1_dat <= w2_dat;
      w2_v   <= w3_v;
      w2_adr <= w3_adr;
      w2_dat <= w3_dat;
      w3_v   <= is_write;
      w3_adr <= adr_i;
      w3_dat <= dat_i;

      // stall high on the two edges after an accepted write (E+1, E+2)
      stall_o <= w2_v | w3_v;
    end
  end

endmodule