stream-frame-hold

module TopModule (
    input             clk,
    input             rst,
    input             wr_i,
    input      [31:0] wr_data,
    input             wr_last_i,
    output            wr_ready_o,
    output reg        m_tvalid_o,
    output reg [31:0] m_tdata_o,
    output reg        m_tlast_o,
    input             m_tready_i
);

    // Depth-8 FIFO storage
    reg [31:0] mem      [0:7];
    reg        mem_last [0:7];
    reg [2:0]  head, tail;
    reg [3:0]  count;

    wire full  = (count == 4'd8);
    wire empty = (count == 4'd0);

    // Ready when FIFO is not full (deasserted during reset)
    assign wr_ready_o = !full && !rst;

    // Pad tracking: pads still to be loaded (0..2) and the last payload data
    reg [1:0]  pads_left;
    reg [31:0] last_pl;

    // Write-side push
    wire do_push = wr_i && !full && !rst;

    // Stream transfer / load control
    wire xfer      = m_tvalid_o && m_tready_i;
    wire have_work = (pads_left != 2'd0) || !empty;
    wire load_new  = !m_tvalid_o && have_work;          // load only when reg free
    wire do_pop    = load_new && (pads_left == 2'd0) && !empty;

    always @(posedge clk) begin
        if (rst) begin
            head       <= 3'd0;
            tail       <= 3'd0;
            count      <= 4'd0;
            m_tvalid_o <= 1'b0;
            m_tdata_o  <= 32'd0;
            m_tlast_o  <= 1'b0;
            pads_left  <= 2'd0;
            last_pl    <= 32'd0;
        end else begin
            // Push a write beat into the FIFO
            if (do_push) begin
                mem[tail]      <= wr_data;
                mem_last[tail] <= wr_last_i;
                tail           <= tail + 3'd1;
            end

            // Accepted transfer: drop valid (creates the idle cycle)
            if (xfer) begin
                m_tvalid_o <= 1'b0;
            end

            // Load the next beat only when the output register is already free
            if (load_new) begin
                m_tvalid_o <= 1'b1;
                if (pads_left != 2'd0) begin
                    // Emit a pad beat
                    m_tdata_o <= last_pl ^ 32'h0BADF00D;
                    m_tlast_o <= (pads_left == 2'd1);   // tlast on second pad only
                    pads_left <= pads_left - 2'd1;
                end else begin
                    // Emit a FIFO payload beat (tlast always 0)
                    m_tdata_o <= mem[head];
                    m_tlast_o <= 1'b0;
                    head      <= head + 3'd1;
                    if (mem_last[head]) begin
                        pads_left <= 2'd2;
                        last_pl   <= mem[head];
                    end
                end
            end

            // Update occupancy once, accounting for both push and pop
            count <= count + (do_push ? 4'd1 : 4'd0) - (do_pop ? 4'd1 : 4'd0);
        end
    end

endmodule