coprocessor-dispatcher-classmix

module TopModule (
    input  logic        clk,
    input  logic        rst,
    input  logic        op_valid_i,
    input  logic [1:0]  op_class_i,
    input  logic [1:0]  op_rd_i,
    input  logic [15:0] op_data_i,
    input  logic        c2_done_i,
    output logic        op_accept_o,
    output logic        wb_valid_o,
    output logic [1:0]  wb_rd_o,
    output logic [15:0] wb_data_o,
    output logic        c2_busy_o,
    output logic [3:0]  inflight_o
);

    // ---------------- slot state ----------------
    logic        occ0, occ1, occ2;
    logic [1:0]  rd0, rd1, rd2;
    logic [15:0] data0, data1, data2;
    logic [1:0]  t1;    // cycles remaining until class-1 result is ready
    logic        rdy2;  // sticky ready flag for class-2

    // ---------------- ready signals ----------------
    logic ready0, ready1, ready2;
    always_comb begin
        ready0 = occ0;                  // class-0 ready the cycle after accept
        ready1 = occ1 & (t1 == 2'd0);   // class-1 ready two cycles after accept
        ready2 = occ2 & rdy2;           // class-2 ready once c2_done seen
    end

    // ---------------- writeback selection (priority 0 > 1 > 2) ----------------
    logic sel0, sel1, sel2;
    always_comb begin
        sel0 = ready0;
        sel1 = ready1 & ~ready0;
        sel2 = ready2 & ~ready0 & ~ready1;

        wb_valid_o = ~rst & (ready0 | ready1 | ready2);
        if (sel0) begin
            wb_rd_o   = rd0;
            wb_data_o = data0;
        end else if (sel1) begin
            wb_rd_o   = rd1;
            wb_data_o = data1;
        end else begin
            wb_rd_o   = rd2;
            wb_data_o = data2;
        end
    end

    // ---------------- accept logic (combinational) ----------------
    logic slot_empty, dest_free, accept;
    always_comb begin
        slot_empty = 1'b0;
        case (op_class_i)
            2'd0:    slot_empty = ~occ0;
            2'd1:    slot_empty = ~occ1;
            2'd2:    slot_empty = ~occ2;
            default: slot_empty = 1'b0;  // class 3 has no slot
        endcase
        dest_free = ~inflight_o[op_rd_i];
        accept    = ~rst & op_valid_i & (op_class_i != 2'd3) & slot_empty & dest_free;
    end

    assign op_accept_o = accept;
    assign c2_busy_o   = ~rst & occ2;

    // ---------------- sequential update ----------------
    always_ff @(posedge clk) begin
        if (rst) begin
            occ0 <= 1'b0; occ1 <= 1'b0; occ2 <= 1'b0;
            rd0  <= 2'd0; rd1  <= 2'd0; rd2  <= 2'd0;
            data0 <= 16'd0; data1 <= 16'd0; data2 <= 16'd0;
            t1   <= 2'd0; rdy2 <= 1'b0;
            inflight_o <= 4'd0;
        end else begin
            // class-1 latency timer
            if (occ1 && (t1 != 2'd0))
                t1 <= t1 - 2'd1;

            // class-2 readiness: sticky, set on any edge with c2_done while busy
            if (occ2 && c2_done_i)
                rdy2 <= 1'b1;

            // writeback: free selected slot, clear its inflight bit
            if (wb_valid_o) begin
                if (sel0) begin
                    occ0 <= 1'b0;
                    inflight_o[rd0] <= 1'b0;
                end else if (sel1) begin
                    occ1 <= 1'b0;
                    inflight_o[rd1] <= 1'b0;
                end else begin
                    occ2 <= 1'b0;
                    rdy2 <= 1'b0;
                    inflight_o[rd2] <= 1'b0;
                end
            end

            // accept: store request, set inflight bit
            if (accept) begin
                case (op_class_i)
                    2'd0: begin
                        occ0  <= 1'b1;
                        rd0   <= op_rd_i;
                        data0 <= op_data_i + 16'd1;
                        inflight_o[op_rd_i] <= 1'b1;
                    end
                    2'd1: begin
                        occ1  <= 1'b1;
                        rd1   <= op_rd_i;
                        data1 <= op_data_i << 1;
                        t1    <= 2'd1;
                        inflight_o[op_rd_i] <= 1'b1;
                    end
                    2'd2: begin
                        occ2  <= 1'b1;
                        rd2   <= op_rd_i;
                        data2 <= op_data_i ^ 16'hffff;
                        rdy2  <= 1'b0;
                        inflight_o[op_rd_i] <= 1'b1;
                    end
                    default: ;
                endcase
            end
        end
    end
endmodule