coprocessor-dispatcher-classmix

module TopModule (
    input               clk,
    input               rst,
    input               op_valid_i,
    input        [1:0]  op_class_i,
    input        [1:0]  op_rd_i,
    input        [15:0] op_data_i,
    input               c2_done_i,
    output              op_accept_o,
    output reg          wb_valid_o,
    output reg   [1:0]  wb_rd_o,
    output reg   [15:0] wb_data_o,
    output              c2_busy_o,
    output reg   [3:0]  inflight_o
);

    // ---------------- Slot state ----------------
    reg         c0_valid;
    reg  [1:0]  c0_rd;
    reg  [15:0] c0_data;

    reg         c1_valid, c1_ready;
    reg  [1:0]  c1_rd;
    reg  [15:0] c1_data;

    reg         c2_valid, c2_ready;
    reg  [1:0]  c2_rd;
    reg  [15:0] c2_data;

    // ---------------- Combinational accept ----------------
    wire cls0 = (op_class_i == 2'b00);
    wire cls1 = (op_class_i == 2'b01);
    wire cls2 = (op_class_i == 2'b10);

    wire slot_empty = (cls0 & ~c0_valid) |
                      (cls1 & ~c1_valid) |
                      (cls2 & ~c2_valid);

    assign op_accept_o = ~rst & op_valid_i & (op_class_i != 2'b11) &
                         ~inflight_o[op_rd_i] & slot_empty;

    wire acc  = op_accept_o;
    wire acc0 = acc & cls0;
    wire acc1 = acc & cls1;
    wire acc2 = acc & cls2;

    // c2 is busy exactly while its slot is occupied
    assign c2_busy_o = ~rst & c2_valid;

    // ---------------- Combinational arbitration ----------------
    wire rdy0 = c0_valid;      // class 0 ready as soon as it is valid
    wire rdy1 = c1_ready;
    wire rdy2 = c2_ready;

    wire wb_fire = rdy0 | rdy1 | rdy2;

    reg        sel0, sel1, sel2;
    reg [1:0]  win_rd;
    reg [15:0] win_data;
    always @(*) begin
        sel0 = 1'b0; sel1 = 1'b0; sel2 = 1'b0;
        win_rd = 2'b00; win_data = 16'h0000;
        if (rdy0) begin
            sel0 = 1'b1; win_rd = c0_rd; win_data = c0_data;
        end else if (rdy1) begin
            sel1 = 1'b1; win_rd = c1_rd; win_data = c1_data;
        end else if (rdy2) begin
            sel2 = 1'b1; win_rd = c2_rd; win_data = c2_data;
        end
    end

    // ---------------- Sequential logic ----------------
    always @(posedge clk) begin
        if (rst) begin
            c0_valid <= 1'b0; c0_rd <= 2'b0; c0_data <= 16'h0;
            c1_valid <= 1'b0; c1_ready <= 1'b0; c1_rd <= 2'b0; c1_data <= 16'h0;
            c2_valid <= 1'b0; c2_ready <= 1'b0; c2_rd <= 2'b0; c2_data <= 16'h0;
            inflight_o <= 4'b0;
            wb_valid_o <= 1'b0;
            wb_rd_o    <= 2'b0;
            wb_data_o  <= 16'h0;
        end else begin
            // Registered writeback outputs (one-cycle pulse)
            wb_valid_o <= wb_fire;
            wb_rd_o    <= win_rd;
            wb_data_o  <= win_data;

            // Slot 0: data+1, ready the cycle after accept
            if (acc0) begin
                c0_valid <= 1'b1;
                c0_rd    <= op_rd_i;
                c0_data  <= op_data_i + 16'd1;
            end else if (c0_valid && sel0) begin
                c0_valid <= 1'b0;
            end

            // Slot 1: data*2, ready one further cycle after becoming valid
            if (acc1) begin
                c1_valid <= 1'b1;
                c1_ready <= 1'b0;
                c1_rd    <= op_rd_i;
                c1_data  <= op_data_i << 1;
            end else if (c1_valid) begin
                if (sel1) begin
                    c1_valid <= 1'b0;
                    c1_ready <= 1'b0;
                end else begin
                    c1_ready <= 1'b1;   // becomes / stays ready (sticky)
                end
            end

            // Slot 2: data^ffff, ready once c2_done_i seen while busy (sticky)
            if (acc2) begin
                c2_valid <= 1'b1;
                c2_ready <= 1'b0;
                c2_rd    <= op_rd_i;
                c2_data  <= op_data_i ^ 16'hffff;
            end else if (c2_valid) begin
                if (sel2) begin
                    c2_valid <= 1'b0;
                    c2_ready <= 1'b0;
                end else if (c2_done_i) begin
                    c2_ready <= 1'b1;   // sticky until writeback fires
                end
            end

            // Inflight tracking: writeback clears its dest, accept sets its dest
            // (these always target distinct bits, so both may apply)
            if (wb_fire) inflight_o[win_rd] <= 1'b0;
            if (acc)     inflight_o[op_rd_i] <= 1'b1;
        end
    end

endmodule