bus-slave-abort-ack

module TopModule(
  input        clk,
  input        rst,
  input        cyc_i,
  input        stb_i,
  input        we_i,
  input  [1:0] adr_i,
  input  [15:0] dat_i,
  output reg   stall_o,
  output reg   ack_o,
  output reg [15:0] dat_o
);

  // Registered slot storage and primed flags
  reg [15:0] slots [0:3];
  reg [3:0]  primed;

  // Read response pipeline (latency 2)
  reg        s2_v, s1_v;
  reg [15:0] s2_d, s1_d;

  // Write commit/response pipeline (latency 3)
  reg        w3_v, w2_v, w1_v;
  reg [1:0]  w3_a, w2_a, w1_a;
  reg [15:0] w3_dat, w2_dat, w1_dat;

  // mix(a,x): pack, into lane k, the bit-reversed source lane (k+a) mod 4
  function [15:0] mix;
    input [1:0]  a;
    input [15:0] x;
    integer k;
    integer s;
    reg [3:0] lane;
    reg [3:0] rev;
    begin
      mix = 16'b0;
      for (k = 0; k < 4; k = k + 1) begin
        s = (k + a) & 3;               // (k+a) mod 4
        lane[0] = x[s];                // lane in increasing bit order
        lane[1] = x[s+4];
        lane[2] = x[s+8];
        lane[3] = x[s+12];
        rev[0] = lane[3];              // bit-reversed source lane
        rev[1] = lane[2];
        rev[2] = lane[1];
        rev[3] = lane[0];
        mix[k]    = rev[0];            // pack into result lane k
        mix[k+4]  = rev[1];
        mix[k+8]  = rev[2];
        mix[k+12] = rev[3];
      end
    end
  endfunction

  wire accept   = cyc_i & stb_i & ~stall_o;
  wire acc_rd   = accept & ~we_i;
  wire acc_wr   = accept &  we_i;

  // committed value for the write currently in the final stage
  wire [15:0] wcommit = mix(w1_a, slots[w1_a]) ^ w1_dat;

  always @(posedge clk) begin
    if (rst) begin
      slots[0] <= 16'b0; slots[1] <= 16'b0;
      slots[2] <= 16'b0; slots[3] <= 16'b0;
      primed   <= 4'b0;
      s2_v <= 1'b0; s1_v <= 1'b0; s2_d <= 16'b0; s1_d <= 16'b0;
      w3_v <= 1'b0; w2_v <= 1'b0; w1_v <= 1'b0;
      w3_a <= 2'b0; w2_a <= 2'b0; w1_a <= 2'b0;
      w3_dat <= 16'b0; w2_dat <= 16'b0; w1_dat <= 16'b0;
      stall_o <= 1'b0; ack_o <= 1'b0; dat_o <= 16'b0;
    end else begin
      // ---- read pipeline shift + load ----
      s1_v <= s2_v;
      s1_d <= s2_d;
      if (acc_rd) begin
        s2_v <= 1'b1;
        s2_d <= primed[adr_i] ? mix(adr_i, slots[adr_i]) : 16'b0;
      end else begin
        s2_v <= 1'b0;
        s2_d <= 16'b0;
      end

      // ---- write pipeline shift + load ----
      w1_v <= w2_v; w1_a <= w2_a; w1_dat <= w2_dat;
      w2_v <= w3_v; w2_a <= w3_a; w2_dat <= w3_dat;
      if (acc_wr) begin
        w3_v   <= 1'b1;
        w3_a   <= adr_i;
        w3_dat <= dat_i;
      end else begin
        w3_v   <= 1'b0;
        w3_a   <= 2'b0;
        w3_dat <= 16'b0;
      end

      // ---- stall: high after E+1 and E+2 for accepted writes ----
      stall_o <= w3_v | w2_v;

      // ---- write commit (always, even if response dropped) ----
      if (w1_v) begin
        slots[w1_a]  <= wcommit;
        primed[w1_a] <= 1'b1;
      end

      // ---- response: read wins on shared edge, ack only if cyc high ----
      if (cyc_i & (s1_v | w1_v)) begin
        ack_o <= 1'b1;
        if (s1_v)
          dat_o <= s1_d;
        else
          dat_o <= wcommit;
      end else begin
        ack_o <= 1'b0;
        dat_o <= 16'b0;
      end
    end
  end

endmodule