apb-lite-slave-regfile

module TopModule(
    input  logic        clk,
    input  logic        rst,
    input  logic        psel,
    input  logic        penable,
    input  logic        pwrite,
    input  logic [3:0]  paddr,
    input  logic [31:0] pwdata,
    output logic [31:0] prdata,
    output logic        pready,
    output logic        pslverr
);

    // Writable storage
    logic [31:0] reg0;   // word 0: normal r/w
    logic [7:0]  reg1;   // word 1: stores only low byte
    logic [31:0] reg3;   // word 3: normal r/w, one wait state

    // Tracks whether the previous cycle was an access cycle of the
    // currently held transaction. Used to insert one wait cycle for word 3.
    logic prev_access;

    wire access = psel & penable;      // access phase this cycle
    wire offmap = (paddr >= 4'd4);     // off-map address

    // prev_access: was the previous cycle an access cycle
    always_ff @(posedge clk) begin
        if (rst)
            prev_access <= 1'b0;
        else
            prev_access <= access;
    end

    // Combinational APB outputs
    always_comb begin
        pready  = 1'b0;
        pslverr = 1'b0;
        prdata  = 32'b0;
        if (!rst && access) begin
            if (offmap) begin
                // Off-map: complete with error, no data
                pready  = 1'b1;
                pslverr = 1'b1;
                prdata  = 32'b0;
            end else begin
                pslverr = 1'b0;
                // Word 3 inserts exactly one wait access cycle
                if (paddr[1:0] == 2'd3)
                    pready = prev_access;
                else
                    pready = 1'b1;
                // Read data present during any mapped read access cycle
                if (!pwrite) begin
                    case (paddr[1:0])
                        2'd0: prdata = reg0;
                        2'd1: prdata = {24'd0, reg1};
                        2'd2: prdata = 32'h0AB15001;
                        2'd3: prdata = reg3;
                    endcase
                end
            end
        end
    end

    // Register updates: only on a completing write access (pready & !pslverr)
    always_ff @(posedge clk) begin
        if (rst) begin
            reg0 <= 32'b0;
            reg1 <= 8'b0;
            reg3 <= 32'b0;
        end else if (access && !offmap && pwrite && pready && !pslverr) begin
            case (paddr[1:0])
                2'd0: reg0 <= pwdata;
                2'd1: reg1 <= pwdata[7:0];
                2'd2: ; // word 2 is read-only: write accepted but ignored
                2'd3: reg3 <= pwdata;
            endcase
        end
    end

endmodule