stream-frame-hold

module TopModule (
    input  wire        clk,
    input  wire        rst,
    input  wire        wr_i,
    input  wire [31:0] wr_data,
    input  wire        wr_last_i,
    output wire        wr_ready_o,
    output wire        m_tvalid_o,
    output wire [31:0] m_tdata_o,
    output wire        m_tlast_o,
    input  wire        m_tready_i
);

    // FIFO storage (depth 8)
    reg [31:0] mem_data [0:7];
    reg        mem_last [0:7];
    reg [2:0]  head;
    reg [2:0]  tail;
    reg [3:0]  count;

    // Stream master registers
    reg        v;            // m_tvalid_o
    reg [31:0] d;            // m_tdata_o
    reg        l;            // m_tlast_o
    reg        cur_last;     // last flag of the beat currently loaded on the stream
    reg [31:0] last_payload; // data of last payload carrying wr_last_i=1
    reg [1:0]  pad_count;    // number of pad beats still to emit (0..2)

    assign wr_ready_o = (count != 4'd8);
    assign m_tvalid_o = v;
    assign m_tdata_o  = d;
    assign m_tlast_o  = l;

    // Write push / FIFO pop conditions
    wire push    = wr_i && wr_ready_o;
    wire xfer    = v && m_tready_i;
    wire fifo_pop = (!v) && (pad_count == 2'd0) && (count != 4'd0);

    integer i;

    always @(posedge clk) begin
        if (rst) begin
            head         <= 3'd0;
            tail         <= 3'd0;
            count        <= 4'd0;
            v            <= 1'b0;
            d            <= 32'd0;
            l            <= 1'b0;
            cur_last     <= 1'b0;
            last_payload <= 32'd0;
            pad_count    <= 2'd0;
            for (i = 0; i < 8; i = i + 1) begin
                mem_data[i] <= 32'd0;
                mem_last[i] <= 1'b0;
            end
        end else begin
            // FIFO write
            if (push) begin
                mem_data[tail] <= wr_data;
                mem_last[tail] <= wr_last_i;
                tail           <= tail + 3'd1;
            end

            // Stream master
            if (xfer) begin
                // Accepted beat: deassert valid. If it was a last-flagged
                // payload, schedule 2 pad beats before the next FIFO beat.
                v <= 1'b0;
                if (cur_last)
                    pad_count <= 2'd2;
            end else if (!v) begin
                if (pad_count != 2'd0) begin
                    // Load a pad beat.
                    v         <= 1'b1;
                    d         <= last_payload ^ 32'h0BAD_F00D;
                    l         <= (pad_count == 2'd1) ? 1'b1 : 1'b0;
                    cur_last  <= 1'b0;
                    pad_count <= pad_count - 2'd1;
                end else if (count != 4'd0) begin
                    // Load the next FIFO payload beat.
                    v            <= 1'b1;
                    d            <= mem_data[head];
                    l            <= 1'b0;
                    cur_last     <= mem_last[head];
                    last_payload <= mem_data[head];
                    head         <= head + 3'd1;
                end
            end
            // else (v && !ready): hold the beat unchanged.

            // Update occupancy once, accounting for push and pop together.
            count <= count + (push ? 4'd1 : 4'd0) - (fifo_pop ? 4'd1 : 4'd0);
        end
    end

endmodule