debug-halt-step-fsm

module TopModule (
    input  logic       clk,
    input  logic       rst,
    input  logic       halt_req_i,
    input  logic       resume_req_i,
    input  logic       step_req_i,
    input  logic       dbus_ren_i,
    input  logic [1:0] dbus_addr_i,
    output logic [7:0] dbus_rdata_o,
    output logic       halted_o,
    output logic       fetch_o
);

    // FSM states
    localparam logic [1:0] RUN  = 2'd0, // running: fetch high, not halted
                           HREQ = 2'd1, // halt pending (extra pipeline stage)
                           HALT = 2'd2, // halted: fetch low, halted high
                           STEP = 2'd3;  // single-step: fetch high for one cycle

    logic [1:0] state, nstate;

    // Next-state logic
    always_comb begin
        nstate = state;
        unique case (state)
            RUN:  nstate = halt_req_i ? HREQ : RUN;
            HREQ: nstate = HALT;                       // unconditional second stage
            HALT: begin
                if (halt_req_i)        nstate = HALT;  // stays halted (covers halt+step)
                else if (resume_req_i) nstate = RUN;
                else if (step_req_i)   nstate = STEP;
                else                   nstate = HALT;
            end
            STEP: nstate = HALT;                       // one-cycle pulse, then re-halt
            default: nstate = RUN;
        endcase
    end

    // Output values per state
    function automatic logic fetch_of(input logic [1:0] s);
        unique case (s)
            RUN, HREQ, STEP: fetch_of = 1'b1;
            default:         fetch_of = 1'b0;
        endcase
    endfunction

    function automatic logic halted_of(input logic [1:0] s);
        halted_of = (s == HALT);
    endfunction

    // Debug bus memory
    function automatic logic [7:0] mem_of(input logic [1:0] a);
        unique case (a)
            2'd0:    mem_of = 8'h5A;
            2'd1:    mem_of = 8'hC3;
            2'd2:    mem_of = 8'h0F;
            2'd3:    mem_of = 8'h96;
            default: mem_of = 8'h00;
        endcase
    endfunction

    // Sequential logic: all outputs registered, synchronous active-high reset
    always_ff @(posedge clk) begin
        if (rst) begin
            state        <= RUN;
            fetch_o      <= 1'b0;
            halted_o     <= 1'b0;
            dbus_rdata_o <= 8'h00;
        end else begin
            state    <= nstate;
            fetch_o  <= fetch_of(nstate);
            halted_o <= halted_of(nstate);

            // Registered read; holds previous value while ren low
            if (dbus_ren_i)
                dbus_rdata_o <= mem_of(dbus_addr_i);
        end
    end

endmodule