serial-break-resync

// UART receiver.
//
// Line idles high. A byte is: one low start bit, eight data bits (LSB first),
// one high stop bit, each BITLEN clock cycles.
//
//  - rx_i is synchronized through two flops; all logic uses that line.
//  - A start is accepted the exact cycle a fresh low run (from the high->low
//    edge) reaches floor(BITLEN/2). Data bits are sampled at bit-period
//    centers, then the stop bit; sampling the stop bit pulses valid_o with the
//    byte on data_o (frame_err_o that cycle if the stop bit was low).
//  - break_o is a level: high once the line completes six continuous low bit
//    periods, until the line is high again. A break preempts any in-progress
//    frame (dropped, no valid). After break_o falls, no start is accepted until
//    the line holds high for six bit periods (any low restarts the count).
//  - d = data bits sampled by the interrupted byte (0 if none); the next d
//    delivered bytes are forced frame_err_o high. A further break replaces any
//    pending count with its own d.
module TopModule #(
    parameter int BITLEN = 16
)(
    input  logic       clk,
    input  logic       rst,
    input  logic       rx_i,
    output logic [7:0] data_o,
    output logic       valid_o,
    output logic       frame_err_o,
    output logic       break_o
);

    localparam int HALF     = BITLEN/2;      // floored half bit period
    localparam int BREAKLEN = 6*BITLEN;      // six continuous bit periods

    localparam logic [1:0] NORMAL  = 2'd0,
                           BRK     = 2'd1,
                           RECOVER = 2'd2;

    logic        sync0, sync1;               // two-flop synchronizer
    logic [1:0]  mode;
    logic [31:0] low_run_r, high_run_r;      // consecutive low/high run lengths
    logic        receiving;
    logic [31:0] cnt;                        // cycles until next sample
    logic [3:0]  bit_no;                     // data bits sampled so far (0..8)
    logic [7:0]  shiftreg;
    logic [3:0]  forced_remaining;           // pending frame_err-forced bytes

    // Combinational temporaries used only inside the clocked block.
    logic        rx;
    logic [31:0] run, hrun;

    always @(posedge clk) begin
        if (rst) begin
            sync0            <= 1'b1;
            sync1            <= 1'b1;
            mode             <= NORMAL;
            low_run_r        <= '0;
            high_run_r       <= '0;
            receiving        <= 1'b0;
            cnt              <= '0;
            bit_no           <= '0;
            shiftreg         <= '0;
            forced_remaining <= '0;
            data_o           <= '0;
            valid_o          <= 1'b0;
            frame_err_o      <= 1'b0;
            break_o          <= 1'b0;
        end else begin
            // Two-flop synchronizer; act on the stable (previous) sync1 value.
            sync0 <= rx_i;
            sync1 <= sync0;
            rx = sync1;

            // Consecutive low / high run lengths, including this cycle.
            run  = rx ? 32'd0 : (low_run_r  + 32'd1);
            hrun = rx ? (high_run_r + 32'd1) : 32'd0;
            low_run_r  <= run;
            high_run_r <= hrun;

            // Pulse outputs default low each cycle.
            valid_o     <= 1'b0;
            frame_err_o <= 1'b0;

            case (mode)
                NORMAL: begin
                    if (run >= BREAKLEN) begin
                        // Break preempts everything, including any live frame.
                        mode             <= BRK;
                        break_o          <= 1'b1;
                        forced_remaining <= receiving ? bit_no : 4'd0;
                        receiving        <= 1'b0;
                    end else if (receiving) begin
                        if (cnt == 0) begin
                            if (bit_no < 8) begin
                                // Sample a data bit at its center.
                                shiftreg[bit_no] <= rx;
                                bit_no           <= bit_no + 4'd1;
                                cnt              <= BITLEN-1;
                            end else begin
                                // Sample the stop bit -> deliver the byte.
                                valid_o   <= 1'b1;
                                data_o    <= shiftreg;
                                if (!rx || forced_remaining != 0)
                                    frame_err_o <= 1'b1;
                                if (forced_remaining != 0)
                                    forced_remaining <= forced_remaining - 4'd1;
                                receiving <= 1'b0;
                            end
                        end else begin
                            cnt <= cnt - 32'd1;
                        end
                    end else begin
                        // Idle: accept a start once the low run reaches HALF.
                        if (run == HALF) begin
                            receiving <= 1'b1;
                            cnt       <= BITLEN-1;
                            bit_no    <= '0;
                            shiftreg  <= '0;
                        end
                    end
                end

                BRK: begin
                    // Hold break_o high until the line returns high.
                    if (rx) begin
                        break_o <= 1'b0;
                        mode    <= RECOVER;
                    end
                end

                RECOVER: begin
                    // No start accepted until six continuous high bit periods;
                    // any low restarts the count (hrun), break_o stays low.
                    if (hrun >= BREAKLEN)
                        mode <= NORMAL;
                end

                default: mode <= NORMAL;
            endcase
        end
    end
endmodule