bus-slave-abort-ack

module TopModule (
    input             clk,
    input             rst,
    input             cyc_i,
    input             stb_i,
    input             we_i,
    input      [1:0]  adr_i,
    input      [15:0] dat_i,
    output reg        stall_o,
    output reg        ack_o,
    output reg [15:0] dat_o
);

    // Slot storage and primed bits
    reg [15:0] slots [0:3];
    reg [3:0]  primed;

    // Read pipeline (latency 2)
    reg        rd1_v,  rd2_v;
    reg [1:0]  rd1_adr, rd2_adr;
    reg        rd1_p,  rd2_p;
    reg [15:0] rd1_val, rd2_val;

    // Write pipeline (latency 3)
    reg        wr1_v,  wr2_v,  wr3_v;
    reg [1:0]  wr1_adr, wr2_adr, wr3_adr;
    reg [15:0] wr1_dat, wr2_dat, wr3_dat;

    integer i;

    // mix(a,x): into lane k, pack the bit-reversed source lane (k+a) mod 4.
    // Lane k occupies bits {k, k+4, k+8, k+12} in increasing bit order.
    function [15:0] mix;
        input [1:0]  a;
        input [15:0] x;
        integer k;
        reg [1:0] s;
        begin
            mix = 16'd0;
            for (k = 0; k < 4; k = k + 1) begin
                s = k + a;                 // (k+a) mod 4 via 2-bit truncation
                mix[k]      = x[s + 12];   // bit-reversed source lane
                mix[k + 4]  = x[s + 8];
                mix[k + 8]  = x[s + 4];
                mix[k + 12] = x[s];
            end
        end
    endfunction

    // Combinational helpers (pre-edge values)
    reg        accept;
    reg        is_read;
    reg        is_write;
    reg        read_fire;
    reg        write_fire;
    reg [15:0] read_data;
    reg [15:0] committed;

    always @(posedge clk) begin
        if (rst) begin
            for (i = 0; i < 4; i = i + 1)
                slots[i] <= 16'd0;
            primed  <= 4'd0;

            rd1_v <= 1'b0; rd2_v <= 1'b0;
            wr1_v <= 1'b0; wr2_v <= 1'b0; wr3_v <= 1'b0;

            stall_o <= 1'b0;
            ack_o   <= 1'b0;
            dat_o   <= 16'd0;
        end else begin
            // Acceptance uses pre-edge stall_o
            accept   = cyc_i & stb_i & ~stall_o;
            is_read  = accept & ~we_i;
            is_write = accept &  we_i;

            // Response firing (pre-edge pipeline values)
            read_fire  = rd2_v;
            write_fire = wr3_v;

            read_data  = rd2_p ? mix(rd2_adr, rd2_val) : 16'd0;
            committed  = mix(wr3_adr, slots[wr3_adr]) ^ wr3_dat;

            // Drive registered response outputs (read wins on shared edge)
            if (read_fire) begin
                ack_o <= cyc_i;
                dat_o <= cyc_i ? read_data : 16'd0;
            end else if (write_fire) begin
                ack_o <= cyc_i;
                dat_o <= cyc_i ? committed : 16'd0;
            end else begin
                ack_o <= 1'b0;
                dat_o <= 16'd0;
            end

            // Write commit happens regardless of cyc_i (dropped writes still commit)
            if (write_fire) begin
                slots[wr3_adr]  <= committed;
                primed[wr3_adr] <= 1'b1;
            end

            // Advance read pipeline
            rd2_v   <= rd1_v;
            rd2_adr <= rd1_adr;
            rd2_p   <= rd1_p;
            rd2_val <= rd1_val;

            rd1_v   <= is_read;
            rd1_adr <= adr_i;
            rd1_p   <= primed[adr_i];
            rd1_val <= slots[adr_i];

            // Advance write pipeline
            wr3_v   <= wr2_v;
            wr3_adr <= wr2_adr;
            wr3_dat <= wr2_dat;

            wr2_v   <= wr1_v;
            wr2_adr <= wr1_adr;
            wr2_dat <= wr1_dat;

            wr1_v   <= is_write;
            wr1_adr <= adr_i;
            wr1_dat <= dat_i;

            // stall_o high the two cycles following a write acceptance
            stall_o <= wr1_v | wr2_v;
        end
    end

endmodule