dualmaster-membridge

module TopModule(
  input         clk,
  input         rst,
  input         a_req_i,
  input  [7:0]  a_addr_i,
  output reg    a_ack_o,
  output reg [15:0] a_data_o,
  input         b_req_i,
  input  [7:0]  b_addr_i,
  output reg    b_ack_o,
  output reg [15:0] b_data_o,
  output reg    m_req_o,
  output reg [7:0] m_addr_o,
  input  [15:0] m_data_i
);

  localparam [2:0] IDLE  = 3'd0,
                   ISSUE = 3'd1,
                   W1    = 3'd2,
                   W2    = 3'd3,
                   ACK   = 3'd4;

  reg [2:0] state;

  // Requests/addresses registered one cycle (so a fresh request is sampled
  // one idle cycle after it first appears -> that sample edge is E).
  reg        ra, rb;
  reg [7:0]  aa, ab;

  reg        last;  // who won the last op: 0 = A, 1 = B
  reg        hot;   // next IDLE sample is the anti-starvation (post-op) sample

  // Combinational arbitration for an IDLE sample.
  reg        do_issue;  // a requester is selected
  reg        win;       // selected requester: 0 = A, 1 = B

  always @(*) begin
    do_issue = 1'b0;
    win      = 1'b0;
    if (ra || rb) begin
      do_issue = 1'b1;
      if (hot) begin
        // Prefer the requester that did NOT just win; else the one that did.
        if (last == 1'b0) begin
          // A won last -> prefer B
          win = rb ? 1'b1 : 1'b0;
        end else begin
          // B won last -> prefer A
          win = ra ? 1'b0 : 1'b1;
        end
      end else begin
        // Cold sample: favour A.
        win = ra ? 1'b0 : 1'b1;
      end
    end
  end

  always @(posedge clk) begin
    if (rst) begin
      state    <= IDLE;
      ra <= 1'b0; rb <= 1'b0;
      aa <= 8'd0; ab <= 8'd0;
      last <= 1'b0; hot <= 1'b0;
      m_req_o  <= 1'b0;
      m_addr_o <= 8'd0;
      a_ack_o  <= 1'b0;
      a_data_o <= 16'd0;
      b_ack_o  <= 1'b0;
      b_data_o <= 16'd0;
    end else begin
      // Register requester inputs every cycle.
      ra <= a_req_i;
      rb <= b_req_i;
      aa <= a_addr_i;
      ab <= b_addr_i;

      // Registered-output defaults (single-cycle pulses).
      m_req_o <= 1'b0;
      a_ack_o <= 1'b0;
      b_ack_o <= 1'b0;

      case (state)
        IDLE: begin
          if (do_issue) begin
            m_req_o  <= 1'b1;                 // command during E+1 only
            m_addr_o <= win ? ab : aa;
            last     <= win;
            state    <= ISSUE;
          end else begin
            hot   <= 1'b0;                    // idle stretch resets arbitration
            state <= IDLE;
          end
        end

        ISSUE: begin                          // E+1
          state <= W1;
        end

        W1: begin                             // E+2
          state <= W2;
        end

        W2: begin                             // E+3: m_data_i valid, capture it
          if (last == 1'b0) begin
            a_ack_o  <= 1'b1;
            a_data_o <= m_data_i;
          end else begin
            b_ack_o  <= 1'b1;
            b_data_o <= m_data_i;
          end
          state <= ACK;
        end

        ACK: begin                            // E+4: ack high one cycle
          hot   <= 1'b1;                       // E+5 sample is anti-starvation
          state <= IDLE;
        end

        default: state <= IDLE;
      endcase
    end
  end

endmodule