stream-frame-hold

module TopModule(
    input  wire        clk,
    input  wire        rst,
    input  wire        wr_i,
    input  wire [31:0] wr_data,
    input  wire        wr_last_i,
    output wire        wr_ready_o,
    output reg         m_tvalid_o,
    output reg  [31:0] m_tdata_o,
    output reg         m_tlast_o,
    input  wire        m_tready_i
);

    localparam [31:0] MAGIC = 32'h0BADF00D;

    // ---------------- FIFO storage (depth 8, {last, data}) ----------------
    reg  [32:0] mem [0:7];
    reg  [2:0]  wptr;
    reg  [2:0]  rptr;
    reg  [3:0]  count;

    wire full  = (count == 4'd8);
    wire empty = (count == 4'd0);

    // ready when not full (and forced low during reset so outputs are clean)
    assign wr_ready_o = (!rst) && (!full);

    wire do_push = wr_i && wr_ready_o;

    wire [32:0] fifo_dout = mem[rptr];

    // ---------------- Output (AXI-Stream master) side ----------------
    reg        is_pad;             // current loaded beat is a pad
    reg        payload_last;       // current payload beat carried wr_last_i=1
    reg [1:0]  pad_remaining;      // pad beats still to emit (0..2)
    reg [31:0] last_payload_data;  // data of most recent payload (for pad calc)

    wire xfer = m_tvalid_o && m_tready_i;

    // A new beat may only be loaded while the stream is idle (m_tvalid low).
    wire can_load_pad     = (pad_remaining != 2'd0);
    wire can_load_payload = (pad_remaining == 2'd0) && (!empty);
    wire do_load = (m_tvalid_o == 1'b0) && (can_load_pad || can_load_payload);
    wire do_pop  = do_load && (pad_remaining == 2'd0); // popping a FIFO payload

    always @(posedge clk) begin
        if (rst) begin
            wptr              <= 3'd0;
            rptr              <= 3'd0;
            count             <= 4'd0;
            m_tvalid_o        <= 1'b0;
            m_tdata_o         <= 32'd0;
            m_tlast_o         <= 1'b0;
            is_pad            <= 1'b0;
            payload_last      <= 1'b0;
            pad_remaining     <= 2'd0;
            last_payload_data <= 32'd0;
        end else begin
            // ---- FIFO occupancy: single update covering push and pop ----
            if (do_push) begin
                mem[wptr] <= {wr_last_i, wr_data};
                wptr      <= wptr + 3'd1;
            end
            if (do_pop) begin
                rptr <= rptr + 3'd1;
            end
            count <= count + (do_push ? 4'd1 : 4'd0) - (do_pop ? 4'd1 : 4'd0);

            // ---- Stream output: registered, one idle cycle between beats ----
            if (xfer) begin
                // accept current beat -> deassert
                m_tvalid_o <= 1'b0;
                if (is_pad) begin
                    pad_remaining <= pad_remaining - 2'd1;
                end else begin
                    if (payload_last)
                        pad_remaining <= 2'd2;
                end
            end else if (do_load) begin
                m_tvalid_o <= 1'b1;
                if (can_load_pad) begin
                    // pad beat
                    m_tdata_o <= last_payload_data ^ MAGIC;
                    m_tlast_o <= (pad_remaining == 2'd1); // 1 only on 2nd pad
                    is_pad    <= 1'b1;
                end else begin
                    // payload beat
                    m_tdata_o         <= fifo_dout[31:0];
                    m_tlast_o         <= 1'b0;            // payloads always 0
                    is_pad            <= 1'b0;
                    payload_last      <= fifo_dout[32];
                    last_payload_data <= fifo_dout[31:0];
                end
            end
        end
    end

endmodule