bus-slave-abort-ack

module TopModule (
    input        clk,
    input        rst,
    input        cyc_i,
    input        stb_i,
    input        we_i,
    input  [1:0] adr_i,
    input [15:0] dat_i,
    output reg        stall_o,
    output reg        ack_o,
    output reg [15:0] dat_o
);

    // Slot storage and primed bits
    reg [15:0] slot [0:3];
    reg        primed [0:3];

    // In-flight request pipeline.
    // Stage 1/2/3 hold requests accepted 1/2/3 edges ago (post-shift view).
    reg        v1, v2, v3;   // valid
    reg        w1, w2, w3;   // is_write
    reg  [1:0] a1, a2, a3;   // captured adr
    reg [15:0] d1, d2, d3;   // captured dat_i (writes)
    reg [15:0] p1, p2, p3;   // captured read payload

    integer i;

    // Combinational temporaries
    reg        accept;
    reg [15:0] cap_payload;
    reg        rd_resp, wr_resp;
    reg [15:0] wr_newval;

    // mix(a,x): into lane k place the bit-reversed source lane (k+a) mod 4.
    // Lane j bits are x[j], x[j+4], x[j+8], x[j+12] in increasing bit order.
    function [15:0] mix;
        input  [1:0] a;
        input [15:0] x;
        integer k;
        integer s;
        begin
            mix = 16'h0000;
            for (k = 0; k < 4; k = k + 1) begin
                s = (k + a) % 4;
                mix[k]      = x[s + 12];
                mix[k + 4]  = x[s + 8];
                mix[k + 8]  = x[s + 4];
                mix[k + 12] = x[s];
            end
        end
    endfunction

    always @(posedge clk) begin
        if (rst) begin
            for (i = 0; i < 4; i = i + 1) begin
                slot[i]   <= 16'h0000;
                primed[i] <= 1'b0;
            end
            v1 <= 1'b0; v2 <= 1'b0; v3 <= 1'b0;
            w1 <= 1'b0; w2 <= 1'b0; w3 <= 1'b0;
            a1 <= 2'b00; a2 <= 2'b00; a3 <= 2'b00;
            d1 <= 16'h0000; d2 <= 16'h0000; d3 <= 16'h0000;
            p1 <= 16'h0000; p2 <= 16'h0000; p3 <= 16'h0000;
            stall_o <= 1'b0;
            ack_o   <= 1'b0;
            dat_o   <= 16'h0000;
        end else begin
            // Pre-edge (current-state) computations
            accept      = cyc_i & stb_i & ~stall_o;
            cap_payload = primed[adr_i] ? mix(adr_i, slot[adr_i]) : 16'h0000;
            rd_resp     = v2 & ~w2;                    // read responds from stage 2 (E+2)
            wr_resp     = v3 &  w3;                    // write commits from stage 3 (E+3)
            wr_newval   = mix(a3, slot[a3]) ^ d3;      // committed slot value

            // Pipeline shift
            v3 <= v2; w3 <= w2; a3 <= a2; d3 <= d2; p3 <= p2;
            v2 <= v1; w2 <= w1; a2 <= a1; d2 <= d1; p2 <= p1;

            // Accept new request into stage 1
            v1 <= accept;
            w1 <= we_i;
            a1 <= adr_i;
            d1 <= dat_i;
            p1 <= cap_payload;

            // Stall: high while an accepted write occupies stage 1 or 2
            // (i.e. after E+1 and E+2 for a write accepted at E).
            stall_o <= (v1 & w1) | (v2 & w2);

            // Write commit is unconditional (dropped writes still commit).
            if (wr_resp) begin
                slot[a3]   <= wr_newval;
                primed[a3] <= 1'b1;
            end

            // Response outputs (0 outside active response edges / when cyc low)
            ack_o <= 1'b0;
            dat_o <= 16'h0000;
            if (cyc_i & (rd_resp | wr_resp)) begin
                ack_o <= 1'b1;
                if (rd_resp)
                    dat_o <= p2;          // read data wins on shared edge
                else
                    dat_o <= wr_newval;   // write returns committed slot
            end
        end
    end

endmodule

module tb;
  reg clk=0, rst=1, cyc_i=0, stb_i=0, we_i=0;
  reg [1:0] adr_i=0;
  reg [15:0] dat_i=0;
  wire stall_o, ack_o;
  wire [15:0] dat_o;

  TopModule d(clk,rst,cyc_i,stb_i,we_i,adr_i,dat_i,stall_o,ack_o,dat_o);

  always #5 clk=~clk;

  // reference mix
  function [15:0] mix; input [1:0] a; input [15:0] x; integer k,s; begin
    mix=0;
    for(k=0;k<4;k=k+1) begin s=(k+a)%4;
      mix[k]=x[s+12]; mix[k+4]=x[s+8]; mix[k+8]=x[s+4]; mix[k+12]=x[s]; end
  end endfunction

  task step; begin @(posedge clk); #1; end endtask

  reg [15:0] D, expw, expr;
  initial begin
    // reset a couple cycles
    @(posedge clk); #1; @(posedge clk); #1; rst=0;
    D=16'hABCD;

    // ---- WRITE to slot 0 accepted at E ----
    // Ensure stall low, drive request
    cyc_i=1; stb_i=1; we_i=1; adr_i=0; dat_i=D;
    @(posedge clk); // this is E (accept, since pre-edge stall low)
    #1;
    // deassert stb but keep cyc high so responses can land
    stb_i=0; we_i=0;
    // after E: stall should be low
    if(stall_o!==1'b0) $display("FAIL stall after E = %b (exp 0)",stall_o);
    @(posedge clk); #1; // E+1
    if(stall_o!==1'b1) $display("FAIL stall after E+1 = %b (exp 1)",stall_o);
    @(posedge clk); #1; // E+2
    if(stall_o!==1'b1) $display("FAIL stall after E+2 = %b (exp 1)",stall_o);
    // E+3: commit + response
    @(posedge clk); #1;
    expw = (mix(0,16'h0000) ^ D);
    if(ack_o!==1'b1) $display("FAIL write ack at E+3 = %b",ack_o);
    if(dat_o!==expw) $display("FAIL write resp = %h exp %h",dat_o,expw);
    else $display("PASS write resp = %h",dat_o);
    if(stall_o!==1'b0) $display("FAIL stall after E+3 = %b (exp 0)",stall_o);

    // idle a bit
    @(posedge clk);#1; @(posedge clk);#1;

    // ---- READ slot 0 ----
    cyc_i=1; stb_i=1; we_i=0; adr_i=0; dat_i=0;
    @(posedge clk); #1; // E (accept read)
    stb_i=0;
    @(posedge clk); #1; // E+1
    if(ack_o!==1'b0) $display("FAIL read ack early at E+1");
    @(posedge clk); #1; // E+2 response
    expr = mix(0, expw); // slot0 now holds expw, primed
    if(ack_o!==1'b1) $display("FAIL read ack at E+2 = %b",ack_o);
    if(dat_o!==expr) $display("FAIL read resp = %h exp %h",dat_o,expr);
    else $display("PASS read resp = %h",dat_o);

    // ---- READ unprimed slot 1 ----
    @(posedge clk);#1;
    cyc_i=1; stb_i=1; we_i=0; adr_i=1;
    @(posedge clk);#1; stb_i=0;
    @(posedge clk);#1;
    @(posedge clk);#1; // E+2
    if(dat_o!==16'h0000) $display("FAIL unprimed read = %h exp 0000",dat_o);
    else $display("PASS unprimed read = %h",dat_o);

    // ---- dropped response: read but cyc low at response ----
    @(posedge clk);#1;
    cyc_i=1; stb_i=1; we_i=0; adr_i=0;
    @(posedge clk);#1; stb_i=0; // accepted read at E
    cyc_i=0; // drop cyc before responses
    @(posedge clk);#1;
    @(posedge clk);#1; // E+2, cyc low
    if(ack_o!==1'b0 || dat_o!==16'h0000) $display("FAIL dropped read ack=%b dat=%h",ack_o,dat_o);
    else $display("PASS dropped read (ack=0,dat=0)");

    $display("DONE");
    $finish;
  end
endmodule

module tb2;
  reg clk=0, rst=1, cyc_i=0, stb_i=0, we_i=0;
  reg [1:0] adr_i=0; reg [15:0] dat_i=0;
  wire stall_o, ack_o; wire [15:0] dat_o;
  TopModule d(clk,rst,cyc_i,stb_i,we_i,adr_i,dat_i,stall_o,ack_o,dat_o);
  always #5 clk=~clk;
  function [15:0] mix; input [1:0] a; input [15:0] x; integer k,s; begin
    mix=0; for(k=0;k<4;k=k+1) begin s=(k+a)%4;
      mix[k]=x[s+12]; mix[k+4]=x[s+8]; mix[k+8]=x[s+4]; mix[k+12]=x[s]; end
  end endfunction
  reg [15:0] D, expw, laterrd;
  initial begin
    @(posedge clk);#1;@(posedge clk);#1; rst=0;
    D=16'h1234;
    // Write slot2 accepted at E; pre-edge stall low
    cyc_i=1; stb_i=1; we_i=1; adr_i=2; dat_i=D;
    @(posedge clk);#1;           // E: write accepted
    // At E+1 stall is still low (write stall shows AFTER E+1), so accept a read
    we_i=0; adr_i=2;             // read slot2
    @(posedge clk);#1;           // E+1: read accepted (pre-edge stall low)
    stb_i=0;
    @(posedge clk);#1;           // E+2
    // E+3: read(from E+1) and write(from E) share this edge
    @(posedge clk);#1;
    // read captured slot2 at E+1 -> unprimed -> 0 ; read wins dat_o
    if(ack_o!==1'b1) $display("FAIL shared ack=%b",ack_o);
    if(dat_o!==16'h0000) $display("FAIL shared dat=%h exp 0000 (read wins, unprimed)",dat_o);
    else $display("PASS shared-edge read wins dat=%h",dat_o);
    // Now confirm the write still committed: read slot2 again
    @(posedge clk);#1;@(posedge clk);#1;
    cyc_i=1; stb_i=1; we_i=0; adr_i=2;
    @(posedge clk);#1; stb_i=0;
    @(posedge clk);#1;
    @(posedge clk);#1;           // E+2 response
    expw = mix(2,16'h0000) ^ D;  // committed slot2 value
    laterrd = mix(2, expw);
    if(dat_o!==laterrd) $display("FAIL write-committed readback=%h exp %h",dat_o,laterrd);
    else $display("PASS write committed despite shared edge, readback=%h",dat_o);
    $display("DONE"); $finish;
  end
endmodule