dualmaster-membridge

module TopModule(
  input  logic        clk,
  input  logic        rst,
  input  logic        a_req_i,
  input  logic [7:0]  a_addr_i,
  output logic        a_ack_o,
  output logic [15:0] a_data_o,
  input  logic        b_req_i,
  input  logic [7:0]  b_addr_i,
  output logic        b_ack_o,
  output logic [15:0] b_data_o,
  output logic        m_req_o,
  output logic [7:0]  m_addr_o,
  input  logic [15:0] m_data_i
);

  // FSM phases relative to the sample edge E:
  //   SAMPLE = E        (idle, arbitrate)
  //   B1     = E+1      (m_req_o/m_addr_o drive the chosen command)
  //   B2     = E+2      (idle bus)
  //   B3     = E+3      (m_data_i valid on the bus)
  //   B4     = E+4      (winner ack + data presented)
  //   next   = E+5      (back to a SAMPLE edge, or IDLE if nothing pending)
  localparam [2:0] IDLE   = 3'd0,
                   SAMPLE = 3'd1,
                   B1     = 3'd2,
                   B2     = 3'd3,
                   B3     = 3'd4,
                   B4     = 3'd5;

  logic [2:0] state;
  logic       post;   // this SAMPLE immediately follows an operation
  logic       cur_a;  // winner of the current/just-finished operation (1 = A)
  logic       ra, rb; // registered requests
  logic [7:0] aa, ba; // registered addresses

  always_ff @(posedge clk) begin
    logic la, lb, dl, wa;

    if (rst) begin
      state    <= IDLE;
      post     <= 1'b0;
      cur_a    <= 1'b0;
      ra       <= 1'b0;
      rb       <= 1'b0;
      aa       <= 8'd0;
      ba       <= 8'd0;
      m_req_o  <= 1'b0;
      m_addr_o <= 8'd0;
      a_ack_o  <= 1'b0;
      a_data_o <= 16'd0;
      b_ack_o  <= 1'b0;
      b_data_o <= 16'd0;
    end else begin
      // register the requester inputs (one idle cycle before they are sampled)
      ra <= a_req_i;
      rb <= b_req_i;
      aa <= a_addr_i;
      ba <= b_addr_i;

      // registered outputs default to their idle values each cycle
      m_req_o  <= 1'b0;
      m_addr_o <= 8'd0;
      a_ack_o  <= 1'b0;
      a_data_o <= 16'd0;
      b_ack_o  <= 1'b0;
      b_data_o <= 16'd0;

      la = ra;
      lb = rb;
      dl = 1'b0;
      wa = 1'b0;

      case (state)
        IDLE: begin
          // a freshly registered request pends here; sample it on the next edge
          if (ra || rb) begin
            state <= SAMPLE;
            post  <= 1'b0;
          end
        end

        SAMPLE: begin
          if (post) begin
            if (cur_a) begin
              // A just won -> prefer B, otherwise A again
              if (lb)      begin wa = 1'b0; dl = 1'b1; end
              else if (la) begin wa = 1'b1; dl = 1'b1; end
            end else begin
              // B just won -> prefer A, otherwise B again
              if (la)      begin wa = 1'b1; dl = 1'b1; end
              else if (lb) begin wa = 1'b0; dl = 1'b1; end
            end
          end else begin
            // cold sample after an idle stretch -> favour A
            if (la)      begin wa = 1'b1; dl = 1'b1; end
            else if (lb) begin wa = 1'b0; dl = 1'b1; end
          end

          if (dl) begin
            state    <= B1;
            m_req_o  <= 1'b1;
            m_addr_o <= wa ? aa : ba;
            cur_a    <= wa;
          end else begin
            state <= IDLE;
          end
        end

        B1: state <= B2;
        B2: state <= B3;

        B3: begin
          state <= B4;
          if (cur_a) begin
            a_ack_o  <= 1'b1;
            a_data_o <= m_data_i;
          end else begin
            b_ack_o  <= 1'b1;
            b_data_o <= m_data_i;
          end
        end

        B4: begin
          state <= SAMPLE;
          post  <= 1'b1;
        end

        default: state <= IDLE;
      endcase
    end
  end

endmodule