Wait-state register-file completer

Chunk ID: 83eaf3
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Output:
/work
apb_core/rtl/apb_slave.sv
apb_core/rtl/apb_pkg.sv
apb_core/rtl/apb_top.sv

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Output:
/bin/bash: line 1: git: command not found

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Output:
//==============================================================================
// apb_slave.sv
//
// Wait-state register-file completer for a two-phase select/enable handshake.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and the state registers are provided. The
//  handshake control, the wait-cycle counting, the register file commit and
//  the outputs are left as a TODO and currently drive constant zeros, so the
//  completer never raises pready and the verifier FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the
//  module name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module apb_slave #(
    parameter AW   = 6,
    parameter DW   = 32,
    parameter NREG = 16
) (
    input  logic                  pclk,
    input  logic                  presetn,
    input  logic                  psel,
    input  logic                  penable,
    input  logic                  pwrite,
    input  logic [AW-1:0]         paddr,
    input  logic [DW-1:0]         pwdata,
    output logic                  pready,
    output logic [DW-1:0]         prdata,
    output logic                  pslverr
);

  // ---------------------------------------------------------------------------
  // State registers (provided). Add whatever combinational helpers you need.
  // ---------------------------------------------------------------------------
  logic [DW-1:0] regfile [0:NREG-1];
  logic [1:0]    state;
  logic [1:0]    acc;        // access-edge counter
  integer        i;

  // ===========================================================================
  // TODO: IMPLEMENT THE COMPLETER.
  //   * walk the two-phase handshake (setup for one clk, then access);
  //   * insert the required number of wait cycles before completing, and pulse
  //     pready for exactly the completion clk;
  //   * commit a write / drive a read on the completion clk per instruction.md;
  //   * flag out-of-range accesses on the completion clk with no register effect;
  //   * presetn is asynchronous, active low, and clears the file and outputs.
  //
  // The placeholder below keeps the module compilable but INCORRECT.
  // ===========================================================================
  always_ff @(posedge pclk or negedge presetn) begin
    if (!presetn) begin
      for (i = 0; i < NREG; i = i + 1) regfile[i] <= {DW{1'b0}};
      state <= 2'd0;
      acc   <= 2'd0;
    end else begin
      // TODO: replace with the real handshake + datapath.
      state <= state;
      acc   <= acc;
    end
  end

  // TODO: replace these placeholder outputs with the real ones.
  assign pready  = 1'b0;
  assign prdata  = {DW{1'b0}};
  assign pslverr = 1'b0;

endmodule : apb_slave

Chunk ID: 03f7d2
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Output:
//==============================================================================
// apb_pkg.sv
//
// Shared geometry for the wait-state register completer. The block exposes a
// register file of NREG words, each DW bits wide, addressed by an AW-bit word
// address. Parameters are declared without an explicit data type for broad
// simulator compatibility (Icarus Verilog 11); they default to integer
// constants, which is sufficient here.
//
// DO NOT change this file.
//==============================================================================
`ifndef APB_PKG_SV
`define APB_PKG_SV

package apb_pkg;

  localparam AW   = 6;    // address width (word address)
  localparam DW   = 32;   // data word width
  localparam NREG = 16;   // number of in-range registers (addr 0..NREG-1)

endpackage : apb_pkg

`endif // APB_PKG_SV

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Output:
//==============================================================================
// apb_top.sv
//
// Thin integration wrapper. The verification environment drives this wrapper so
// that the instantiation wiring is exercised alongside the completer itself. It
// instantiates apb_slave with the project-default geometry from apb_pkg.
//
// DO NOT change this file.
//==============================================================================
`timescale 1ns/1ps
`include "apb_pkg.sv"

module apb_top (
    input  logic                          pclk,
    input  logic                          presetn,
    input  logic                          psel,
    input  logic                          penable,
    input  logic                          pwrite,
    input  logic [apb_pkg::AW-1:0]        paddr,
    input  logic [apb_pkg::DW-1:0]        pwdata,
    output logic                          pready,
    output logic [apb_pkg::DW-1:0]        prdata,
    output logic                          pslverr
);

  // Bare instantiation: the completer carries its own default geometry, so a
  // submission needs no parameter override to elaborate correctly.
  apb_slave u_apb_slave (
      .pclk    (pclk),
      .presetn (presetn),
      .psel    (psel),
      .penable (penable),
      .pwrite  (pwrite),
      .paddr   (paddr),
      .pwdata  (pwdata),
      .pready  (pready),
      .prdata  (prdata),
      .pslverr (pslverr)
  );

endmodule : apb_top

Chunk ID: 256621
Wall time: 0.0000 seconds
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Output:
./rtl/apb_pkg.sv
./rtl/apb_slave.sv
./rtl/apb_top.sv

Chunk ID: 5a8a08
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Process exited with code 0
Original token count: 72
Output:
rtl/apb_top.sv:12: Include file apb_pkg.sv not found
warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- package apb_pkg declared here: rtl/apb_pkg.sv:15

Chunk ID: 62b8f1
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Output:
     1	//==============================================================================
     2	// apb_slave.sv
     3	//
     4	// Wait-state register-file completer for a two-phase select/enable handshake.
     5	//
     6	// ---------------------------------------------------------------------------
     7	//  >>> IMPLEMENTATION REQUIRED <<<
     8	//
     9	//  The module ports, parameters and the state registers are provided. The
    10	//  handshake control, the wait-cycle counting, the register file commit and
    11	//  the outputs are left as a TODO and currently drive constant zeros, so the
    12	//  completer never raises pready and the verifier FAILS.
    13	//
    14	//  Implement the behaviour described in instruction.md. Do NOT change the
    15	//  module name, the port list, or the parameter list.
    16	//
    17	//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
    18	//  function-call result) is a syntax error under `iverilog -g2012`. Index only
    19	//  named signals, and do any bit work that needs an intermediate value inside a
    20	//  `function automatic` using named locals.
    21	// ---------------------------------------------------------------------------
    22	//==============================================================================
    23	`timescale 1ns/1ps
    24	
    25	module apb_slave #(
    26	    parameter AW   = 6,
    27	    parameter DW   = 32,
    28	    parameter NREG = 16
    29	) (
    30	    input  logic                  pclk,
    31	    input  logic                  presetn,
    32	    input  logic                  psel,
    33	    input  logic                  penable,
    34	    input  logic                  pwrite,
    35	    input  logic [AW-1:0]         paddr,
    36	    input  logic [DW-1:0]         pwdata,
    37	    output logic                  pready,
    38	    output logic [DW-1:0]         prdata,
    39	    output logic                  pslverr
    40	);
    41	
    42	  // ---------------------------------------------------------------------------
    43	  // State registers (provided). Add whatever combinational helpers you need.
    44	  // ---------------------------------------------------------------------------
    45	  logic [DW-1:0] regfile [0:NREG-1];
    46	  logic [1:0]    state;
    47	  logic [1:0]    acc;        // access-edge counter
    48	  logic          req_write;
    49	  logic [AW-1:0] req_addr;
    50	  logic [DW-1:0] req_wdata;
    51	  integer        i;
    52	
    53	  localparam ST_IDLE   = 2'd0;
    54	  localparam ST_SETUP  = 2'd1;
    55	  localparam ST_ACCESS = 2'd2;
    56	
    57	  function automatic logic [1:0] wait_count(input logic is_write);
    58	    begin
    59	      wait_count = is_write ? 2'd2 : 2'd1;
    60	    end
    61	  endfunction
    62	
    63	  function automatic logic addr_in_range(input logic [AW-1:0] addr);
    64	    begin
    65	      addr_in_range = (addr < NREG);
    66	    end
    67	  endfunction
    68	
    69	  always_ff @(posedge pclk or negedge presetn) begin
    70	    if (!presetn) begin
    71	      for (i = 0; i < NREG; i = i + 1) regfile[i] <= {DW{1'b0}};
    72	      state     <= ST_IDLE;
    73	      acc       <= 2'd0;
    74	      req_write <= 1'b0;
    75	      req_addr  <= {AW{1'b0}};
    76	      req_wdata <= {DW{1'b0}};
    77	      pready    <= 1'b0;
    78	      prdata    <= {DW{1'b0}};
    79	      pslverr   <= 1'b0;
    80	    end else begin
    81	      pready  <= 1'b0;
    82	      prdata  <= {DW{1'b0}};
    83	      pslverr <= 1'b0;
    84	
    85	      case (state)
    86	        ST_IDLE: begin
    87	          acc <= 2'd0;
    88	          if (psel && !penable) begin
    89	            req_write <= pwrite;
    90	            req_addr  <= paddr;
    91	            req_wdata <= pwdata;
    92	            state     <= ST_SETUP;
    93	          end
    94	        end
    95	
    96	        ST_SETUP: begin
    97	          acc <= 2'd0;
    98	          if (psel && penable) begin
    99	            acc   <= 2'd1;
   100	            state <= ST_ACCESS;
   101	          end else if (psel && !penable) begin
   102	            req_write <= pwrite;
   103	            req_addr  <= paddr;
   104	            req_wdata <= pwdata;
   105	          end else begin
   106	            state <= ST_IDLE;
   107	          end
   108	        end
   109	
   110	        ST_ACCESS: begin
   111	          if (psel && penable) begin
   112	            if (acc == wait_count(req_write)) begin
   113	              pready  <= 1'b1;
   114	              pslverr <= !addr_in_range(req_addr);
   115	              state   <= ST_IDLE;
   116	              acc     <= 2'd0;
   117	
   118	              if (addr_in_range(req_addr)) begin
   119	                if (req_write) begin
   120	                  regfile[req_addr] <= req_wdata;
   121	                end else begin
   122	                  prdata <= regfile[req_addr];
   123	                end
   124	              end
   125	            end else begin
   126	              acc <= acc + 2'd1;
   127	            end
   128	          end else if (psel && !penable) begin
   129	            req_write <= pwrite;
   130	            req_addr  <= paddr;
   131	            req_wdata <= pwdata;
   132	            state     <= ST_SETUP;
   133	            acc       <= 2'd0;
   134	          end else begin
   135	            state <= ST_IDLE;
   136	            acc   <= 2'd0;
   137	          end
   138	        end
   139	
   140	        default: begin
   141	          state <= ST_IDLE;
   142	          acc   <= 2'd0;
   143	        end
   144	      endcase
   145	    end
   146	  end
   147	
   148	endmodule : apb_slave

Chunk ID: add1ca
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Output:
rtl/apb_pkg.sv:15: warning: timescale for apb_pkg inherited from another file.
rtl/apb_top.sv:10: ...: The inherited timescale is here.

Chunk ID: a6f5ce
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Output:
rtl/apb_pkg.sv:15: warning: timescale for apb_pkg inherited from another file.
rtl/apb_top.sv:10: ...: The inherited timescale is here.
PASS

Chunk ID: 6b9c2c
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Output:
rtl/apb_pkg.sv:15: warning: timescale for apb_pkg inherited from another file.
rtl/apb_top.sv:10: ...: The inherited timescale is here.

Chunk ID: 4efbea
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 14
Output:
./rtl/apb_pkg.sv
./rtl/apb_slave.sv
./rtl/apb_top.sv

Chunk ID: e07c95
Wall time: 0.0000 seconds
Process exited with code 0
Original token count: 1170
Output:
//==============================================================================
// apb_slave.sv
//
// Wait-state register-file completer for a two-phase select/enable handshake.
//
// ---------------------------------------------------------------------------
//  >>> IMPLEMENTATION REQUIRED <<<
//
//  The module ports, parameters and the state registers are provided. The
//  handshake control, the wait-cycle counting, the register file commit and
//  the outputs are left as a TODO and currently drive constant zeros, so the
//  completer never raises pready and the verifier FAILS.
//
//  Implement the behaviour described in instruction.md. Do NOT change the
//  module name, the port list, or the parameter list.
//
//  iverilog 11 note: a bit/part-select of an EXPRESSION (a sum, a shift, a
//  function-call result) is a syntax error under `iverilog -g2012`. Index only
//  named signals, and do any bit work that needs an intermediate value inside a
//  `function automatic` using named locals.
// ---------------------------------------------------------------------------
//==============================================================================
`timescale 1ns/1ps

module apb_slave #(
    parameter AW   = 6,
    parameter DW   = 32,
    parameter NREG = 16
) (
    input  logic                  pclk,
    input  logic                  presetn,
    input  logic                  psel,
    input  logic                  penable,
    input  logic                  pwrite,
    input  logic [AW-1:0]         paddr,
    input  logic [DW-1:0]         pwdata,
    output logic                  pready,
    output logic [DW-1:0]         prdata,
    output logic                  pslverr
);

  // ---------------------------------------------------------------------------
  // State registers (provided). Add whatever combinational helpers you need.
  // ---------------------------------------------------------------------------
  logic [DW-1:0] regfile [0:NREG-1];
  logic [1:0]    state;
  logic [1:0]    acc;        // access-edge counter
  logic          req_write;
  logic [AW-1:0] req_addr;
  logic [DW-1:0] req_wdata;
  integer        i;

  localparam ST_IDLE   = 2'd0;
  localparam ST_SETUP  = 2'd1;
  localparam ST_ACCESS = 2'd2;

  function automatic logic [1:0] wait_count(input logic is_write);
    begin
      wait_count = is_write ? 2'd2 : 2'd1;
    end
  endfunction

  function automatic logic addr_in_range(input logic [AW-1:0] addr);
    begin
      addr_in_range = (addr < NREG);
    end
  endfunction

  always_ff @(posedge pclk or negedge presetn) begin
    if (!presetn) begin
      for (i = 0; i < NREG; i = i + 1) regfile[i] <= {DW{1'b0}};
      state     <= ST_IDLE;
      acc       <= 2'd0;
      req_write <= 1'b0;
      req_addr  <= {AW{1'b0}};
      req_wdata <= {DW{1'b0}};
      pready    <= 1'b0;
      prdata    <= {DW{1'b0}};
      pslverr   <= 1'b0;
    end else begin
      pready  <= 1'b0;
      prdata  <= {DW{1'b0}};
      pslverr <= 1'b0;

      case (state)
        ST_IDLE: begin
          acc <= 2'd0;
          if (psel && !penable) begin
            req_write <= pwrite;
            req_addr  <= paddr;
            req_wdata <= pwdata;
            state     <= ST_SETUP;
          end
        end

        ST_SETUP: begin
          acc <= 2'd0;
          if (psel && penable) begin
            acc   <= 2'd1;
            state <= ST_ACCESS;
          end else if (psel && !penable) begin
            req_write <= pwrite;
            req_addr  <= paddr;
            req_wdata <= pwdata;
          end else begin
            state <= ST_IDLE;
          end
        end

        ST_ACCESS: begin
          if (psel && penable) begin
            if (acc == wait_count(req_write)) begin
              pready  <= 1'b1;
              pslverr <= !addr_in_range(req_addr);
              state   <= ST_IDLE;
              acc     <= 2'd0;

              if (addr_in_range(req_addr)) begin
                if (req_write) begin
                  regfile[req_addr] <= req_wdata;
                end else begin
                  prdata <= regfile[req_addr];
                end
              end
            end else begin
              acc <= acc + 2'd1;
            end
          end else if (psel && !penable) begin
            req_write <= pwrite;
            req_addr  <= paddr;
            req_wdata <= pwdata;
            state     <= ST_SETUP;
            acc       <= 2'd0;
          end else begin
            state <= ST_IDLE;
            acc   <= 2'd0;
          end
        end

        default: begin
          state <= ST_IDLE;
          acc   <= 2'd0;
        end
      endcase
    end
  end

endmodule : apb_slave