tests/test.sh exit code (0 → resolved); the classification below is post-hoc and cannot change it.module TopModule (
input logic clk,
input logic rst,
input logic a_req_i,
input logic [7:0] a_addr_i,
output logic a_ack_o,
output logic [15:0] a_data_o,
input logic b_req_i,
input logic [7:0] b_addr_i,
output logic b_ack_o,
output logic [15:0] b_data_o,
output logic m_req_o,
output logic [7:0] m_addr_o,
input logic [15:0] m_data_i
);
// Busy-phase states (E+1 .. E+4)
localparam logic [2:0] IDLE = 3'd0,
BUSY1 = 3'd1, // E+1: command driven
BUSY2 = 3'd2, // E+2
BUSY3 = 3'd3, // E+3: m_data_i valid
BUSY4 = 3'd4; // E+4: ack + data
logic [2:0] state;
logic win; // current op winner: 0 = A, 1 = B
logic last_win; // winner of previous op
logic just_finished; // this idle sample directly follows an op (E+5)
// Registered requests / addresses (one-cycle registration before sampling)
logic a_req_r, b_req_r;
logic [7:0] a_addr_r, b_addr_r;
// Combinational arbitration, consumed only while IDLE
logic launch;
logic sel;
always_comb begin
launch = 1'b0;
sel = 1'b0;
if (just_finished) begin
// sample directly after an operation: prefer the one that did not just win
if (last_win == 1'b0) begin
// A just won -> prefer B
if (b_req_r) begin launch = 1'b1; sel = 1'b1; end
else if (a_req_r) begin launch = 1'b1; sel = 1'b0; end
end else begin
// B just won -> prefer A
if (a_req_r) begin launch = 1'b1; sel = 1'b0; end
else if (b_req_r) begin launch = 1'b1; sel = 1'b1; end
end
end else begin
// cold sample after an idle stretch: prefer A
if (a_req_r) begin launch = 1'b1; sel = 1'b0; end
else if (b_req_r) begin launch = 1'b1; sel = 1'b1; end
end
end
always_ff @(posedge clk) begin
if (rst) begin
state <= IDLE;
win <= 1'b0;
last_win <= 1'b0;
just_finished <= 1'b0;
a_req_r <= 1'b0;
b_req_r <= 1'b0;
a_addr_r <= 8'd0;
b_addr_r <= 8'd0;
a_ack_o <= 1'b0;
b_ack_o <= 1'b0;
a_data_o <= 16'd0;
b_data_o <= 16'd0;
m_req_o <= 1'b0;
m_addr_o <= 8'd0;
end else begin
// register requests/addresses every cycle
a_req_r <= a_req_i;
b_req_r <= b_req_i;
a_addr_r <= a_addr_i;
b_addr_r <= b_addr_i;
// default output values
a_ack_o <= 1'b0;
b_ack_o <= 1'b0;
m_req_o <= 1'b0;
m_addr_o <= 8'd0;
case (state)
IDLE: begin
if (launch) begin
state <= BUSY1;
win <= sel;
m_req_o <= 1'b1;
m_addr_o <= (sel == 1'b0) ? a_addr_r : b_addr_r;
just_finished <= 1'b0;
end else begin
state <= IDLE;
just_finished <= 1'b0; // idle stretch resets fairness -> next is cold
end
end
BUSY1: state <= BUSY2; // E+2
BUSY2: state <= BUSY3; // E+3 (m_data_i valid this cycle)
BUSY3: begin // capture data, raise ack for E+4
state <= BUSY4;
if (win == 1'b0) begin
a_ack_o <= 1'b1;
a_data_o <= m_data_i;
end else begin
b_ack_o <= 1'b1;
b_data_o <= m_data_i;
end
end
BUSY4: begin // E+4 done -> idle at E+5
state <= IDLE;
last_win <= win;
just_finished <= 1'b1;
a_data_o <= 16'd0;
b_data_o <= 16'd0;
end
default: state <= IDLE;
endcase
end
end
endmodule
Lint/compile the SystemVerilog module
(command -v verilator >/dev/null && verilator --lint-only -Wall -Wno-DECLFILENAME dut.sv 2>&1 | head -40 || echo "verilator not found"); (command -v iverilog >/dev/null && iverilog -g2012 -o /tmp/dut.out dut.sv && echo "iverilog OK" || echo "iverilog not found or failed")
verilator not found iverilog OK [stdout] verilator not found iverilog OK
No file changes, the agent left the workspace untouched.
TEST dut_present: PASS (/app/dut.sv exists)
TEST dut_forbidden: PASS (no forbidden constructs)
TEST dut_compiles: PASS (compiled with held-back reference/testbench)
TEST simulation_completed: PASS (Mismatches: 0 in 3839 samples)
TEST reference_equivalence: PASS (all 3839 samples matched reference)
{"score": 1.000000, "results_file": "/tmp/h2t-grader-home.OXcB1I/runtime/cb_verifier_306-2748-29053-30772_306/results.jsonl"}Reproduce this trial: git checkout 2f94510 && PYTHONPATH=src python3 scripts/build_site.py , then open trial/trial_b8a2eccb27cc4451. Re-running the agent live requires EVAL_PLATFORM_ENABLE_OAUTH_SMOKE=1 and is non-deterministic.
Trial trial_b8a2eccb27cc4451 · verifier authoritative; classifier explanatory.