dualmaster-membridge

module TopModule(
  input  logic        clk,
  input  logic        rst,
  input  logic        a_req_i,
  input  logic [7:0]  a_addr_i,
  output logic        a_ack_o,
  output logic [15:0] a_data_o,
  input  logic        b_req_i,
  input  logic [7:0]  b_addr_i,
  output logic        b_ack_o,
  output logic [15:0] b_data_o,
  output logic        m_req_o,
  output logic [7:0]  m_addr_o,
  input  logic [15:0] m_data_i
);

  // Operation pipeline states (cycle labels relative to sample edge E)
  localparam [2:0] IDLE = 3'd0, // E   : idle, arbitration sample
                   CMD  = 3'd1, // E+1 : command driven to memory
                   W1   = 3'd2, // E+2 : wait
                   W2   = 3'd3, // E+3 : m_data_i valid, capture it
                   ACK  = 3'd4;  // E+4 : winner ack + data high

  logic [2:0] st;

  // One-cycle registration of the requester interface.  A fresh request is
  // thus registered one (idle) cycle before it is sampled at E.
  logic       ar_req, br_req;
  logic [7:0] ar_addr, br_addr;

  // Arbitration memory.
  logic win;            // winner of the current/most-recent op (0=A, 1=B)
  logic just_finished;  // 1 only during the idle cycle directly after an op

  // Combinational winner selection.
  logic pending;
  logic chooseB;

  always_comb begin
    pending = ar_req | br_req;
    chooseB = 1'b0;
    if (just_finished) begin
      // Warm sample (E+5, back to back): prefer the requester that did not
      // just win; fall back to the one that did if the other is not asking.
      if (win == 1'b0) begin
        chooseB = br_req ? 1'b1 : 1'b0;   // A just won -> prefer B
      end else begin
        chooseB = ar_req ? 1'b0 : 1'b1;   // B just won -> prefer A
      end
    end else begin
      // Cold sample (after an idle stretch): favour A.
      chooseB = ar_req ? 1'b0 : 1'b1;
    end
  end

  always_ff @(posedge clk) begin
    if (rst) begin
      st            <= IDLE;
      ar_req        <= 1'b0;
      br_req        <= 1'b0;
      ar_addr       <= 8'b0;
      br_addr       <= 8'b0;
      win           <= 1'b0;
      just_finished <= 1'b0;
      a_ack_o       <= 1'b0;
      b_ack_o       <= 1'b0;
      a_data_o      <= 16'b0;
      b_data_o      <= 16'b0;
      m_req_o       <= 1'b0;
      m_addr_o      <= 8'b0;
    end else begin
      // Register the requester interface every cycle.
      ar_req  <= a_req_i;
      br_req  <= b_req_i;
      ar_addr <= a_addr_i;
      br_addr <= b_addr_i;

      // Default output/state each cycle.
      a_ack_o  <= 1'b0;
      b_ack_o  <= 1'b0;
      m_req_o  <= 1'b0;
      m_addr_o <= 8'b0;

      case (st)
        IDLE: begin
          if (pending) begin
            m_req_o       <= 1'b1;
            if (chooseB) begin
              m_addr_o <= br_addr;
              win      <= 1'b1;
            end else begin
              m_addr_o <= ar_addr;
              win      <= 1'b0;
            end
            just_finished <= 1'b0;
            st            <= CMD;
          end else begin
            just_finished <= 1'b0;  // idle stretch -> next sample is cold
            st            <= IDLE;
          end
        end

        CMD: st <= W1;

        W1: st <= W2;

        W2: begin
          // Capture memory word; ack + data appear next cycle (E+4).
          if (win == 1'b0) begin
            a_ack_o  <= 1'b1;
            a_data_o <= m_data_i;
          end else begin
            b_ack_o  <= 1'b1;
            b_data_o <= m_data_i;
          end
          st <= ACK;
        end

        ACK: begin
          // Ack was high this (E+4) cycle; return to idle at E+5, warm.
          just_finished <= 1'b1;
          st            <= IDLE;
        end

        default: st <= IDLE;
      endcase
    end
  end

endmodule