apb-lite-slave-regfile

module TopModule (
    input  logic        clk,
    input  logic        rst,
    input  logic        psel,
    input  logic        penable,
    input  logic        pwrite,
    input  logic [3:0]  paddr,
    input  logic [31:0] pwdata,
    output logic [31:0] prdata,
    output logic        pready,
    output logic        pslverr
);

    // Writable / stored registers
    logic [31:0] reg0, reg3;
    logic [7:0]  reg1;

    // Tracks whether the current word-3 held transaction has already
    // presented its single wait (first access) cycle.
    logic        w3_active;

    // APB phase decode
    wire access = psel & penable;                 // access cycle
    wire offmap = access & (paddr >= 4'd4);        // off-map access
    wire is_w3  = access & (paddr == 4'd3);        // word-3 access

    // ---- pready ----
    always_comb begin
        if (rst)
            pready = 1'b0;
        else if (!access)
            pready = 1'b0;
        else if (offmap)
            pready = 1'b1;                          // off-map completes immediately
        else if (paddr == 4'd3)
            pready = w3_active;                     // one wait cycle for word 3
        else
            pready = 1'b1;                          // words 0,1,2 complete immediately
    end

    // ---- pslverr ----
    always_comb begin
        if (rst)
            pslverr = 1'b0;
        else
            pslverr = offmap;                       // error only on off-map access
    end

    // ---- prdata ----
    always_comb begin
        prdata = 32'd0;
        if (!rst && access && ~pwrite) begin
            case (paddr)
                4'd0: prdata = reg0;
                4'd1: prdata = {24'd0, reg1};
                4'd2: prdata = 32'h0AB1_5001;
                4'd3: prdata = reg3;
                default: prdata = 32'd0;
            endcase
        end
    end

    // Write enable: transfer completes (pready) with no error, and is a write.
    wire wr_en = access & pwrite & pready & ~pslverr;

    always_ff @(posedge clk) begin
        if (rst) begin
            reg0      <= 32'd0;
            reg1      <= 8'd0;
            reg3      <= 32'd0;
            w3_active <= 1'b0;
        end else begin
            // Word-3 wait tracking: clear when the held transaction ends
            // (psel or penable falls), set after any word-3 access cycle so
            // later access cycles of the same transaction report pready=1.
            if (!(psel & penable))
                w3_active <= 1'b0;
            else if (is_w3)
                w3_active <= 1'b1;

            // Register updates
            if (wr_en) begin
                case (paddr)
                    4'd0: reg0 <= pwdata;
                    4'd1: reg1 <= pwdata[7:0];
                    4'd3: reg3 <= pwdata;
                    default: ; // word 2 read-only, off-map: ignore
                endcase
            end
        end
    end

endmodule