stream-frame-hold

module TopModule (
    input  wire        clk,
    input  wire        rst,
    input  wire        wr_i,
    input  wire [31:0] wr_data,
    input  wire        wr_last_i,
    output wire        wr_ready_o,
    output reg         m_tvalid_o,
    output reg  [31:0] m_tdata_o,
    output reg         m_tlast_o,
    input  wire        m_tready_i
);

    // Depth-8 FIFO storing {last, data}
    reg [31:0] mem_data [0:7];
    reg        mem_last [0:7];
    reg [2:0]  wr_ptr;
    reg [2:0]  rd_ptr;
    reg [3:0]  count;      // occupancy 0..8

    // Stream sequencing state
    reg [1:0]  pad_cnt;        // pending pad beats (0,1,2)
    reg [31:0] last_payload;   // data of most recent payload beat

    // Ready when FIFO not full (and not in reset)
    assign wr_ready_o = !rst && (count != 4'd8);

    // Push into FIFO
    wire do_push = wr_i && wr_ready_o;

    // A beat may be loaded only when the output register is idle (valid low).
    // When valid is high an xfer edge deasserts first, so no load that edge.
    wire can_load     = !m_tvalid_o;
    wire load_pad     = can_load && (pad_cnt != 2'd0);
    wire fifo_ne      = (count != 4'd0);
    wire load_payload = can_load && (pad_cnt == 2'd0) && fifo_ne;
    wire do_pop       = load_payload;

    integer i;

    always @(posedge clk) begin
        if (rst) begin
            wr_ptr       <= 3'd0;
            rd_ptr       <= 3'd0;
            count        <= 4'd0;
            m_tvalid_o   <= 1'b0;
            m_tdata_o    <= 32'd0;
            m_tlast_o    <= 1'b0;
            pad_cnt      <= 2'd0;
            last_payload <= 32'd0;
            for (i = 0; i < 8; i = i + 1) begin
                mem_data[i] <= 32'd0;
                mem_last[i] <= 1'b0;
            end
        end else begin
            // FIFO write
            if (do_push) begin
                mem_data[wr_ptr] <= wr_data;
                mem_last[wr_ptr] <= wr_last_i;
                wr_ptr           <= wr_ptr + 3'd1;
            end

            // Stream output register discipline
            if (m_tvalid_o && m_tready_i) begin
                // xfer: deassert, hold data/last
                m_tvalid_o <= 1'b0;
            end else if (!m_tvalid_o) begin
                if (pad_cnt != 2'd0) begin
                    // emit pad beat
                    m_tdata_o  <= last_payload ^ 32'h0BAD_F00D;
                    m_tlast_o  <= (pad_cnt == 2'd1);
                    m_tvalid_o <= 1'b1;
                    pad_cnt    <= pad_cnt - 2'd1;
                end else if (fifo_ne) begin
                    // pop payload beat
                    m_tdata_o    <= mem_data[rd_ptr];
                    m_tlast_o    <= 1'b0;
                    m_tvalid_o   <= 1'b1;
                    last_payload <= mem_data[rd_ptr];
                    rd_ptr       <= rd_ptr + 3'd1;
                    if (mem_last[rd_ptr])
                        pad_cnt <= 2'd2;
                end
            end

            // Occupancy: single update covers both push and pop this edge
            count <= count + (do_push ? 4'd1 : 4'd0) - (do_pop ? 4'd1 : 4'd0);
        end
    end

endmodule